KR19980058396A - High voltage semiconductor device and manufacturing method thereof - Google Patents

Abstract

The present invention provides a high voltage semiconductor device and a method of manufacturing the same, which can increase the breakdown voltage of the junction while simplifying the process by forming a junction region through a stepped gate pattern to reduce the mask process. The high voltage semiconductor device may include a semiconductor substrate having a predetermined device isolation layer; A gate insulating film formed on the substrate between the device isolation films; A gate formed such that the first to third conductive films are sequentially stacked on the gate insulating film, and the first and second conductive films and the third conductive film have a predetermined step shape; A high concentration impurity region formed in the substrate on both sides of the gate and spaced apart from the gate by a predetermined portion, a low concentration impurity region formed in the substrate on both sides of the first or second conductive film of the gate and surrounding the high concentration impurity region; And a junction region of a source and a drain formed in the substrate on both sides of the third conductive film and composed of the lowest concentration impurity region overlapping the gate.

Description

High voltage semiconductor device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a high voltage semiconductor device and a method for manufacturing the same, capable of driving a high current to improve the operation speed of the device.

In general, when an external system using high voltage is controlled by an integrated circuit, the integrated circuit needs an element for high voltage control therein, and such an element needs a structure having a high breakdown voltage. .

That is, in the drain of the transistor to which the high voltage is directly applied, the punch-through voltage between the drain and the substrate and the breakdown voltage between the drain and the well are applied to enable the external system to operate smoothly. It must be greater than the high voltage. Therefore, in order to obtain a high breakdown voltage as described above, conventionally, the device is formed in a structure having a low concentration layer of the same conductivity type as the drain under the drain, but a device capable of driving a high voltage by changing the structure of the device is manufactured. It was.

However, as described above, as the structure of the device is changed for driving a high voltage, there is a problem in that the process becomes complicated as an additional mask process is additionally increased.

Accordingly, the present invention has been made in view of the above-described problems, and forms a junction region through a stepped gate pattern, thereby simplifying the process by reducing the mask process and increasing the breakdown voltage of the junction. And its manufacturing method.

1A to 1E are sequential cross-sectional views illustrating a high voltage semiconductor device and a method of manufacturing the same according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

1: semiconductor substrate, 2 a field oxide film, 3: a gate insulating film, 4 to 6: The first to third amorphous silicon film, 7: mask pattern, 8: n ^- impurity region, 9: n ^- impurity region 10: n ⁺ impurity region, 100: junction region, 200: gate

A high voltage semiconductor device according to the present invention for achieving the above object is a semiconductor substrate provided with a predetermined device isolation film; A gate insulating film formed on the substrate between the device isolation layers; A gate formed such that first to third conductive films are sequentially stacked on the gate insulating film, and the first and second conductive films and the third conductive film have a predetermined step shape; A high concentration impurity region formed in the substrate on both sides of the gate and spaced apart from the gate by a predetermined portion, and a low concentration impurity region in the substrate on both sides of the first or second conductive film of the gate and surrounding the high concentration impurity region And a junction region of a source and a drain formed in the substrate on both sides of the third conductive film of the gate and composed of the lowest concentration impurity region overlapping the gate.

In addition, a method of manufacturing a high voltage semiconductor device according to the present invention for achieving the above object comprises the steps of forming a gate insulating film on a semiconductor substrate formed with a device isolation film thereon; Sequentially forming first to third conductive layers having different etching selectivities on the gate insulating layer; First etching the third to first conductive layer patterns to expose portions of both substrates of the gate predetermined region between the device isolation layers; Second etching the first etched second and third conductive layers to pattern the first to third conductive layers in a predetermined step shape; A low concentration impurity region is formed in the substrates on both sides of the third conductive film pattern and a low concentration impurity region in the substrates on both sides of the second conductive film pattern, and a high concentration impurity region is formed in the substrates on both sides of the first conductive film pattern. Forming a junction region of the source and the drain; And forming a gate by third etching using a gate mask in the form of the second conductive layer pattern to remove the conductive layer on both sides of the gate predetermined region and the first conductive layer of the gate pattern. do.

The etching selectivity may be an etching selectivity with respect to the second etching, and the first to third conductive layers may be amorphous silicon films formed in an in-situ manner.

The first amorphous silicon film may be an undoped amorphous silicon film, and the second and third amorphous silicon films may be amorphous silicon films doped with a predetermined concentration of impurities.

In addition, the first and second etching may be performed using the same etching mask.

In addition, the forming of the junction region may include: implanting first ions into the substrate with first impurity ions; Forming a minimum and low concentration impurity region, by implanting a second ion into the substrate; And heat-treating for activating the impurities.

The first ion implantation process may be performed such that the peak value of the ion implantation energy is present in a region where the protruding portion of the second conductive film pattern patterned in the step form and the lower first conductive film pattern are in contact with each other. In the ion implantation process, the ion implantation energy is set so as not to pass through the first conductive layer pattern patterned in the step shape.

According to the present invention having the above structure, the junction region of the source and the drain of the device is formed in the structure of the lowest concentration, the low concentration, and the high concentration impurity region, thereby increasing the breakdown voltage of the junction and the lowest concentration impurity region completely with the gate. Overlap can increase the current driving force. In addition, as the ion implantation process is performed using the conductive pattern patterned in the step shape, the mask process may be reduced.

EXAMPLE

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

1A through 1E are cross-sectional views sequentially illustrating a method of manufacturing a high voltage transistor according to an exemplary embodiment of the present invention.

First, as shown in FIG. 1A, a gate oxide film 3 is formed on a semiconductor substrate 1 on which a field oxide film 2 for element isolation is formed. Subsequently, an undoped first amorphous silicon film 4 is deposited on the gate oxide film 3 to a thickness of 450 to 550 GPa, and P is doped thereon at a concentration of 1 × 10 ¹⁸ to 9 × 10 ¹⁸ / cm 3. A third amorphous silicon film 5 having a thickness of 600 to 800 GPa and doped with P at a concentration of 1 × 10 ²⁰ to 9 × 10 ²⁰ on the second amorphous silicon film 5 (6) is formed to a thickness of 2,000 to 3,000 kPa. In this case, the first to third amorphous silicon films 4 to 6 are formed using an in-situ doped polysilicon film deposition apparatus.

Then, the first to third amorphous silicon films 4 to 6 are heat treated at a temperature of 600 to 700 ° C. for 50 to 70 minutes to select wet etching of the first to third amorphous silicon films 4 to 6. To increase the degree. That is, as the impurities of the second and third amorphous silicon films 5 and 6 doped with P are activated by the heat treatment, the wet etching selectivity of the first to third amorphous silicon films 4 to 6 is, for example, The wet etch selectivity is increased from 60: 1 to 80: 1 in the HNO ₃ / CH ₃ COOH / HF / DI solution used for subsequent wet etching.

As shown in FIG. 1B, a predetermined mask pattern 7 is formed on the third amorphous silicon film 6 by photolithography. The substrate between the field oxide layer 2 is dry-etched by dry etching the lower third and second amorphous silicon layers 6 and 5 and the first amorphous silicon layer 4 using the mask pattern 7 as an etching mask. Partially exposed.

As shown in FIG. 1C, the wet etching using the HNO ₃ / CH ₃ COOH / HF / DI solution is performed for a predetermined time by using the mask pattern 7 as an etching mask to form the first to third amorphous polysilicon films 4. 6) are patterned in a predetermined step shape. That is, due to the different wet etching selectivity of the second and third amorphous silicon films 5 and 6 according to the doping degree of P, the undoped first amorphous silicon film 4 is not etched and the second to third As the amorphous silicon films 5 and 6 are etched at different etching rates, the first to third amorphous silicon films 4 to 6 are patterned in a predetermined step shape.

As shown in FIG. 1D, the mask pattern 7 is removed by a known method, and a predetermined heat treatment process is performed to recover damage caused by etching. Subsequently, the first ion implantation of P atoms into the substrate 1 causes the n ⁻ impurity region 8 and the n ⁻ impurity region to be formed in the substrate 1 on both sides of the third and second amorphous silicon films 6 and 5. 9) are formed respectively. In this case, the first ion implantation process is performed by setting the peak value of the ion implantation energy to be present in the portion A where the protruding portion of the second amorphous silicon film 5 and the lower portion of the first amorphous silicon film 4 are in contact with each other. As a result, impurity ions implanted into the substrate 1 by the stepped first to third amorphous polysilicon films 4 to 6 are formed at different concentrations.

Thereafter, a high concentration of As ions are implanted into the substrate 1 to form the second ⁺ impurity regions 10 on both sides of the first amorphous silicon film 4. At this time, the ion implantation energy is set so as not to penetrate the first amorphous polysilicon film 4 during the second ion implantation process, whereby the n ⁺ impurity regions 10 are n ⁻ and n ⁻ impurity regions 8, 9. ) To be surrounded by). Subsequently, heat treatment is performed to activate the impurities, thereby completing the junction region 100 of the source and drain where the n ⁻ impurity region 8 overlaps the second amorphous silicon film 5.

As shown in FIG. 1E, dry etching is performed using a predetermined gate mask to form a gate pattern of the actual MOS transistor so that the length of the gate is as long as the length of the second amorphous silicon film 5. In this way, the gate 200 is formed.

According to the embodiment, the junction area of the source and drain of the transistor n ^- as well as to increase the breakdown voltage of the junction, as to form a structure of n ^+, n ^{- -,} n impurity regions gate By completely overlapping with, the current driving force can be increased to improve the operation speed of the device. In addition, as the ion implantation process is performed using an amorphous silicon film patterned in a predetermined step shape, the mask process can be reduced, thereby achieving cost reduction.

In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.

Claims (33)

A semiconductor substrate provided with a predetermined device isolation film; A gate insulating film formed on the substrate between the device isolation layers; A gate formed such that first to third conductive films are sequentially stacked on the gate insulating film, and the first and second conductive films and the third conductive film have a predetermined step shape; A high concentration impurity region formed in the substrate on both sides of the gate and spaced apart from the gate by a predetermined portion, and a low concentration impurity region formed in the substrate on both sides of the first or second conductive film of the gate and surrounding the high concentration impurity region And a junction region of a source and a drain formed in the substrate on both sides of the third conductive film of the gate and composed of the lowest concentration impurity region overlapping the gate. The high voltage semiconductor device of claim 1, wherein the first to third conductive films are amorphous silicon films. 3. The high voltage semiconductor device of claim 2, wherein the first amorphous silicon film is an undoped amorphous silicon film, and the second and third amorphous silicon films are amorphous silicon films doped with a predetermined concentration of impurities. . 4. The high voltage semiconductor device of claim 3, wherein the first amorphous silicon film has a thickness of 450 to 550 kV. 4. The high voltage semiconductor device of claim 3, wherein the second and third amorphous silicon films are amorphous silicon films doped with P at different concentrations. 6. The high voltage semiconductor device of claim 5, wherein the concentration of P doped in the second amorphous silicon film is 1 × 10 ¹⁸ to 9 × 10 ¹⁸ / cm 3. 7. The high voltage semiconductor device of claim 6, wherein the thickness of the second amorphous silicon is 600 to 800 kW. 6. The high voltage semiconductor device of claim 5, wherein the concentration of P doped in the third amorphous silicon film is 1 × 10 ²⁰ to 9 × 10 ²⁰ / cm 3. 9. The high voltage semiconductor device of claim 8, wherein the third amorphous silicon film has a thickness of 2,000 to 3,000 Pa. Forming a gate insulating film on a semiconductor substrate on which an isolation layer is formed; Sequentially forming first to third conductive layers having different etching selectivities on the gate insulating layer; First etching the third to first conductive layer patterns to expose predetermined portions of both substrates of the gate predetermined region between the device isolation layers; Second etching the first etched second and third conductive layers to pattern the first to third conductive layers in a predetermined step shape; A minimum concentration impurity region is formed in the substrates on both sides of the third conductive film pattern, and a low concentration impurity region is formed in the substrates on both sides of the second conductive film pattern, and high concentration impurities are formed in the substrates on both sides of the first conductive film pattern. Forming a junction region of a source and a drain forming a region; And, Forming a gate by third etching using a gate mask in the form of the second conductive layer pattern to remove the conductive layer on both sides of the gate predetermined region and the first conductive layer of the gate pattern; Method of manufacturing a semiconductor device. The method of claim 10, wherein the etching selectivity is an etching selectivity with respect to the upper limb second etching. The method of claim 10, wherein the first to third conductive films are amorphous silicon films. The method of claim 12, wherein the first to third amorphous silicon films are formed in an in-situ manner. 14. The high voltage semiconductor device of claim 13, wherein the first amorphous silicon film is an undoped amorphous silicon film, and the second and third amorphous silicon films are amorphous silicon films doped with different concentrations of predetermined impurities. Manufacturing method. The method of claim 14, wherein the first amorphous silicon film is formed to a thickness of 450 to 550 kV. 15. The method of claim 14, wherein the second and third amorphous silicon films are amorphous silicon films doped with P at different concentrations. The method of claim 16, wherein the concentration of P doped in the second amorphous silicon film is 1 × 10 ¹⁸ to 9 × 10 ¹⁸ / cm 3. 18. The method of claim 17, wherein the second amorphous silicon film is formed to a thickness of 600 to 800 kW. The method of manufacturing a high voltage semiconductor device according to claim 16, wherein the third amorphous silicon film is 1 × 10 ²⁰ to 9 × 10 ²⁰ / cm 3 of P doped with the third amorphous silicon film. 20. The method of claim 19, wherein the third amorphous silicon film is formed to a thickness of 2,000 to 3,000 kV. 15. The method of claim 14, wherein the first to third amorphous polysilicon films have an etch selectivity through a predetermined heat treatment process. The method of claim 21, wherein the heat treatment is performed at a temperature of 600 to 700 ° C. for 50 to 70 minutes. 23. The method of claim 22, wherein the etching selectivity of the first to third amorphous silicon films is 60: 1 to 80: 1. The method of claim 10, wherein the first and second etching are performed using the same etching mask. The method of claim 10, wherein the first etching is performed by dry etching. The method of claim 10, wherein the second etching is performed by wet etching. The method of claim 26, wherein the wet etching is performed using a HNO ₃ / CH ₃ COOH / HF / DI solution. The method of claim 10, wherein the forming of the junction region comprises: implanting first impurity ions into the substrate; Forming a minimum and low concentration impurity region, including implanting second impurity ions into the substrate; And, A method of manufacturing a high voltage semiconductor device comprising the step of heat treatment to activate the impurities. The method of claim 28, wherein the first ion implantation process is performed such that a peak value of ion implantation energy is present in a region where the protruding portion of the second conductive layer pattern patterned in the step form and the lower first conductive layer pattern are folded. A method of manufacturing a high voltage semiconductor device, characterized in that. 30. The method of claim 29, wherein the first impurity is P. 29. The method of claim 28, wherein the ion implantation energy is set so as not to transmit the first conductive layer pattern patterned in the step shape during the second ion implantation process. 32. The method of claim 31, wherein said second impurity is As. The method of claim 10, wherein the third etching is performed by dry etching.