JPS6299977A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To miniaturize the layout area of the titled device by constituting one or plural MOSFETs, to which signals that are always made the same in level are supplied, of serial MOSFETs in plural unit circuits constituting a decoder circuit of one MOSFET. CONSTITUTION:Address signals a0 and a1 are supplied to a pre-decoder circuit PDC 1 and four kinds of pre-decode signals 00-11 are formed. A unit circuit UDCR 1 receives pre-decode signals of driving MOSFETs Q1-Q4 and PDCs 2 and 3 and is constituted of driving MOSFETs Q5 and Q6 which are set to serial forms commonly to each MOSFET Q1-Q4 and precharge MOSFETs Q7-Q10. Decode signals obtained from drains of the FETs Q1-Q4 are outputted as decode output signals W0-W3 through inverter circuits N1-N4. MOSFETs, to which signals that are always set to the same level are supplied, are constituted of one MOSFET Q5 and Q6, thus the number of used elements is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor integrated circuit device, and relates to a technique that is effective for use in devices equipped with a decoder circuit, such as semiconductor memories, for example.

[Background technology]

In a semiconductor memory bag such as RAM (Random Access Memory) or ROM (Read Only Memory), an address decoder is provided to form a selection signal to select one memory cell. These address decoders are composed of, for example, a 2" (II) logic gate circuit that receives an n-bit address signal. As the logic gate circuit, for example, as shown in FIG.
MOSFETs Q20 to Q22 (Q24
~ Q26), the series M OS F E
i' When all of Q20 to Q22 (Q24 to Q26) are turned on, they each form a selection signal. In the circuit shown in the figure, in order to reduce the number of MOSFETs connected in series, predecoder circuits PDCl to P
A predecode signal formed by DC3 is supplied. .

By the way, with the progress of semiconductor technology, elements are being miniaturized, and RAMs with a large storage capacity of approximately 1 Mbit have been developed. With such an increase in storage capacity, a problem arises in that the area occupied by unit circuits that are similar to those of conventional address decoders increases if unit circuits are used.

Regarding the address decoder in the Guinamisoku type RAM, see, for example, Japanese Patent Laid-Open No. 53-41946.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor integrated circuit device including a decoder circuit with a reduced layout area.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a serial drive MOS receives a human input signal consisting of a plurality of bits or its predecoded signal.
Among the series MOSFETs in a plurality of unit circuits including FET and forming a decoder circuit, one or more MOSFETs are supplied with the above-mentioned signal which is always kept at the same level, except for the drive MOSFET t- provided on the output terminal side.
By configuring each OSFET with one MOSFET, the layout area can be reduced. [Embodiment] FIG. 1 shows a circuit diagram of an embodiment of an address decoder circuit according to the present invention. Each circuit element in the same figure is
Although not particularly limited, known CMO5 (complementary MO5)
Integrated circuit manufacturing technology has enabled monocrystalline silicon-like
It is formed on one semiconductor substrate. In the figure, the MOSFET whose channel portion is marked with an arrow is a P-channel portion SFET.

The decoder of this embodiment uses address signals aO to a5, for example, to prevent the drawing from becoming complicated.
It is configured to receive a 6-bit input signal consisting of , and form 64 decoded signals. The figure exemplarily shows two sets of unit circuits UDCR1 and UDCR2, each of which forms four types of decode signals, each consisting of decode signals WO to W3 and W4 to W7.

In this embodiment, although not particularly limited, the decoder circuit is divided into four circuits in total in order not to reduce the number of series MOS FETs for forming one decode signal. That is, address signals aO and al consisting of 2 bits are supplied to the first predecoder circuit PDC1, where four types of decoded signals OO to 11 are formed. Similarly, the address signal a consisting of 2 bits
2. a3 and a4. a5 is supplied to second and third predecoder circuits PDC2 and PDC3, respectively, to form four decoded signals OO to 11, respectively.

The three sets of predecoded signals are supplied to each unit circuit UDCR1, UDCR2, etc. in the set according to a predetermined combination. The unit circuit LIDCR1 basically has four N circuits corresponding to four types of predecode output signals formed by the first predecoder circuit PDCL.
Channel-type drive MO5FETs QI to Q4 and the second and third predecoder circuits PDC2 and PDC
N-channel type drive MOSFETs Q5 and Q receive one predecode signal OO from each of the above-mentioned MOSFETs Q3 and are commonly connected in series to each of the MOSFETs QL to Q4.
6, and a P-channel type precharge MOSFE provided in each of the above MOS FETQ1 to Q4.
It is composed of TQ7 to QIO. The above MOSF
The decoded signals obtained from the drains of ETCl to Q4 are converted into the decoded output signals WO to W via static CMOS inverter circuits N1 to N4.
Output as 3. These decode output signals WO to W3 are supplied to the memory array as, for example, word line selection signals.

The unit circuit UDCR2 forming the other set of decoded output signals W4 to W7 is constituted by an MO5FET circuit similar to the above. However, the second predecoder circuit PDC
2 output signal O1 is the MOS of the unit circuit UDCR1.
The only difference is that it is supplied to the gate of the MOS FET corresponding to FETQ5.

For example, if address signals aO to a5 are all at a low level (logic "0"), each predecoder circuit PDC1 to POC3 sets its respective predecode output signal OO to a high level. With this, M OS F'E
TQl, Q5 and Q6 are in the on state,
A low level selection signal is formed by discharging the precharge voltage at the drain of MOSFETQI. Despite the on-state of the common MOSFETs Q5 and Q6, MOSFETs Q2 to Q4 are connected to the predecode output signals 01 to 11 of the first predecoder circuit PDel.
Since it is turned off by the low level of MOSF
The drains of ETQ2 to Q4 are maintained at the precharge level.

In the other set, the first predecoder circuit PDC1
There is a MOSFET that is turned on by the high level of the decode output signal 00 of the second or third predecoder circuit PDC2 or POC3.
A low level of 1 to 11 determines whether the number of the two serial MOSFETs (both one MOSFET
The SFET is turned off. As a result, all four output signals obtained from all other sets are maintained at the precharge level.

When address signals a1 to a5 are at the same level as above and address signal aO is switched to high level, predecode signal 01 becomes high level and MOS FETQ 2 is turned on instead of MOSFETQI.
Only that drain is discharged to low level. Similarly, when address signals a2 to a5 are at the same level as above, four MOS FETQ1 to Q are selected from the combination of 2-bit address signals aO and al.
4 is turned on to form the above-mentioned low level output signal. In this way, we can transform the high level into logical “
When adopting positive logic with
AND) Operates as a gate circuit.

In this embodiment, only one of the 64 decoded output signals forming the selection signal is discharged to a low level, and all others are left at a high precharge level. This makes it possible to reduce power consumption.

Since the above-mentioned Nant gate circuit itself performs a simple operation, the high level (precharge level) will cause a level drop due to the leakage current of its output node. Although there is no particular restriction, in this embodiment, the To compensate for the level drop, the following MOS F E
T is provided.

Each output node in the unit circuit UDCR1 is provided with P-channel switch MOSFETs Q12 to Q15, which receive the output signals of the CMOS inverter circuits N1 to N4 that send out the output signals, although this is not particularly limited.

These switches MOSFETQI2 to Q15 have their gates constantly connected to the ground potential of the circuit, and are supplied with a minute current generated by a P-channel type current source MOSFETQI1 whose conductance is reduced. Although not particularly limited, this current source MOSF
ETQI l is provided in common to similar switch MOSFETs such as other unit circuits UDCR2 and the like. In this way, when the current source MOSFET QI1 is commonly used for a large number of unit circuits, it is necessary to flow a relatively large current as a whole in order to compensate for the leakage current of each unit circuit. Therefore, the element size can be made smaller than that of a current source MOSFET that generates only a minute current for one unit circuit. That is, in order to form the above-mentioned minute current, the conductance is set to be extremely small, so the channel length of the MOSFET Tr is set to be long, and the area thereof becomes relatively large.

In the above unit circuit UDCRl, the switch MOSF
Among the ETQ12 to Q15, the gates of those set to high level output signals (non-selected level) are turned on by being supplied with low level signals via inverter circuits N1 to N4. This allows the MOS to be connected to the output node of the dynamic Nant gate circuit.
Since the minute current formed by FETQll is supplied, the output signal can be maintained at a high level like the power supply voltage Vcc. Further, if the output signal of the Nant gate circuit is low level (selection level), the CMO
The switch MOSFET is turned off by the high level of the output signal of the S inverter circuit. Thereby, when forming a low level output signal, it is possible to eliminate the consumption of direct current for the level compensation. Thereby, a decoded output signal can be formed by substantially the same operation as a static type circuit.

In this embodiment, among the series MOSFETs that form different decoded output signals, except for those provided on the output terminal side, the MOSFETs to which signals are always supplied to f, which are always at the same level, are combined into one MOSFET. By replacing it with , the number of elements can be reduced. For example, one MOSFET that is common to the four decode outputs that receive the second and third predecode output signals in the above embodiment circuit has a layout that is horizontally long along the output signal line of the predecoder. By arranging them, it is possible to reduce the pitch in the vertical direction in the figure. In addition, since it is only necessary to secure a space for forming one contact for the pre-date output signal line, the pre-decode signal line can be formed with high density. can be made smaller. In addition, the above-mentioned standardized Mo5t'E
A relatively large element formation area can be allocated to TQ5°Q6. This makes it possible to increase the size and increase the discharge current, thereby increasing the speed of operation.

〔effect〕

(1) Series MOS to form different decoded output signals!
? Among the ETs, excluding those provided on the output terminal side, MOSFETs that are always supplied with a signal at the same level can be replaced with a single MOSFET, which can be arranged horizontally in a horizontal direction along the input line, and can be done manually. Since it is only necessary to form one contact for a signal line, input signal lines can be formed with high density. This provides the effect of reducing the area occupied by the address decoder circuit.

(2) A relatively large element formation area can be allocated to the common MOSFET. This allows the size to be increased and the discharge current to be increased, resulting in the effect that the operation speed can be increased.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, series MOS
The number of FET stages can take various embodiments depending on the number of decoded outputs. Further, in addition to the predecode signal, the address signal itself may be supplied to one common MOSFET. That is,
This is because there are combinations in which the address signal set as the upper bit is always set at the same level for a plurality of decoded output signals. Sota, precharge MOS F E
T is the drive MO5FF, the same P4 type MOSFE as T.
It may be composed of T. Further, in addition to the above-mentioned dynamic type circuit, it may be applicable to a ratio type logic circuit. In this case, the load means is a drive MOS F
It is also possible to use an enhancement type MOSFET configured with the same 4-electrode type MOSFET as the ET, or a dipleg g:/ type MOSFET.

[Application field]

This invention is widely applicable to semiconductor memory arrangements such as dynamic RAM, static RAM, ROP, etc., as well as semiconductor integrated circuit devices equipped with various decoding circuits that receive and decode multi-bit input signals. Available.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a decoder circuit according to the present invention, and FIG. 2 is a circuit diagram showing an example of a decoder circuit of this prior art. PDCI-PDC3...Pre-decoder circuit, UDCRI
, tJ, DcR2...unit circuit, N1~N6...inverter circuit

Claims (1)

[Claims] 1. A decoder circuit consisting of a plurality of unit circuits including a series drive MOSFET each receiving an input signal consisting of a plurality of bits or a pre-decoded signal thereof, the series MOSFET in the plurality of unit circuits. A semiconductor integrated circuit device characterized in that, except for a drive MOSFET provided on the output terminal side, each of the one or more MOSFETs to which the above-mentioned signal always kept at the same level is supplied is constituted by one MOSFET. 2. The semiconductor integrated circuit device constitutes a semiconductor memory,
The plurality of unit circuits are precharge MOs of a first conductivity type.
Drive MOSF of second conductivity type in series configuration with SFET
2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is constituted by a dynamic type circuit consisting of an ET.