JPS6193749A - Timing clock extraction circuit - Google Patents

Abstract

PURPOSE:To improve a consecutive zero resistance and to make the titled circuit immune to jitter by providing a circuit detecting that consecutive zero exists in a received pulse signal string and using the output of the said detection circuit to control the amplification factor of a timing preamplifier. CONSTITUTION:If consecutive zero exists in the pulse signal string transmitted from the transmission side, an integration circuit 11 detects the consecutive zero to increase the amplification factor of the timing preamplifier 10. Since the output level of a narrow band filter 3 is increased, the resistance to the consecutive zero is improved and fitter immunity is not deteriorated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a timing clock extraction circuit in digital transmission.

In digital transmission, pulse signals are transmitted, so
On the receiving side, it is necessary to extract a timing clock from the received pulse, and a circuit provided for this purpose is called a timing clock extraction circuit.

[Conventional technology]

FIG. 2 is a diagram showing an example of a conventional timing clock extraction circuit.

In the figure, 1 is an equalization amplifier, 2 is an identification circuit, 3 is a narrowband filter, 4 is a timing clock amplifier, 5 is a received pulse regeneration circuit, and 6 is a frame synchronization circuit. The same symbols represent the same objects throughout the following discussion.

The pulse signal train sent from the transmitting side is equalized by an equalizing amplifier/equalizing circuit 1 for waveform distortion caused by the line, amplified, and input to an identification circuit 2 and a narrow band filter 3.

The narrowband filter 3 has an extremely narrowband filter using approximately 1000 elements, and uses the transmission side clock frequency as its center frequency. The narrowband filter 3 provides its output with the same frequency component as the clock frequency on the transmitting side. This signal is amplified by a timing clock amplifier 4 and used as a clock on the receiving side.

On the other hand, the received pulse signal train is compared with the reference level formed by the identification circuit 2 and becomes a "1" signal or a "0" signal, which is punched out by the above-mentioned clock in the received pulse regeneration circuit 5 and synchronized with the clock. They become a “1” signal and an “O” signal. This output signal is normally sent to a frame synchronization circuit 6, etc., and is used for subsequent reception operations.

[Problem that the invention seeks to solve]

As explained above, in the conventional method, if the pulse signal train sent from the transmitting side contains consecutive "0" signals, the output component of the narrowband filter 3 disappears, resulting in inaccurate clock extraction. Become.

In the past, a narrow band filter with a large Q was used to increase the tolerance when this "0" signal continues (referred to as zero continuous tolerance), but as the Q value increases, the passband width becomes narrower. On the other hand, it has the disadvantage of being susceptible to jitter.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the conventional method and provide a timing clock extraction circuit that has zero-run tolerance and is resistant to jitter.

) [Means for solving the problem] The means for solving the problem is to add “0” to the received pulse signal train.
This is achieved by providing a circuit that detects that the signal is continuous, and controlling the amplification degree of the preamplifier of the narrowband filter for timing clock extraction using the output of the detection circuit.

[Effect]

According to the present invention, when "O" signals are continuous in the received pulse signal train, the amplification degree of the preamplifier of the narrowband filter for timing clock extraction is increased by the output of the zero chain detection circuit, and the narrowband filter is Since the drop in output is compensated for, it is possible to realize a timing clock extraction circuit that has zero-run tolerance and is resistant to jitter.

〔Example〕

FIG. 1 is a diagram showing an embodiment of a timing clock extraction circuit according to the present invention.

In the figure, 10 is a timing preamplifier, and 11 is an integration circuit.

The present invention will be described in detail below with reference to the drawings.

In the present invention, as shown in the figure, a timing preamplifier 10 is placed in front of the conventional narrowband filter 3, and an integrating circuit 11 is further added.

By adding the above circuit, when "0" signals are continuous in the pulse signal train sent from the transmitting side, the integrating circuit 11 detects the continuous zero signal and uses its output to amplify the timing preamplifier 10. The input level of the narrowband filter 3 is increased by increasing the input level. That is, the timing preamplifier 10 operates as a type of variable gain amplifier whose gain is continuously controlled by the output of the integrating circuit 11.

Therefore, when the "0" signal continues, in the conventional system, the output level of the narrowband filter 3 decreases for the reason mentioned above, but the integrating circuit 11 according to the present invention detects the continuous zero signal and increases the amplification level of the timing preamplifier 10. Narrow band filter 3
Since the operation is performed in the direction of increasing the output level of , zero-run tolerance can be increased without increasing the value of Q, so that jitter tolerance does not deteriorate.

〔Effect of the invention〕

As described above in detail, the present invention has the great effect of realizing a timing clock extraction circuit that has zero-run tolerance and is resistant to jitter.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of a timing clock extraction circuit according to the present invention. FIG. 2 is a diagram showing an example of a conventional timing clock extraction circuit. In the figure, 1 is an equalization amplifier, 2 is an identification circuit, 3 is a narrowband filter, 4 is a timing clock amplifier, 5 is a received pulse regeneration circuit, 6 is a frame synchronization circuit, IO is a timing preamplifier, and 11 is an integration circuit. It is.

Claims (1)

[Claims] A timing clock characterized in that a circuit is provided to detect that a "0" signal continues in a received pulse signal train, and the amplification degree of a preamplifier of a narrow band filter for timing clock extraction is controlled by the output of the detection circuit. extraction circuit.