JPS6059814A - Programmable delay circuit and semiconductor integrated circuit device using the same - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a technology that is particularly effective when applied to digital circuits in electronic circuit technology, and is particularly effective when applied to signal processing in digital logic circuits. It is related to technology.

[Background technology]

The present inventor has revealed that there are the following problems with electronic circuit technology, particularly with signal processing technology in digital logic circuits.

That is, in a digital logic circuit, a time delay occurs in the signal as the signal is logically processed, and furthermore, the magnitude of this time delay varies fluidly depending on the design or operating state of the logic circuit. It has been revealed that this causes problems such as unstable operation of digital systems.

Also, in a certain signal processing system or device,
A delay circuit is used to compensate for the signal transmission delay, but since the signal transmission delay changes fluidly,
It was also made clear that the problem would arise that sufficient compensation effects would not be obtained.

This invention has been made by focusing on the above-mentioned problems.

[Purpose of the invention]

An object of the present invention is to enable electrically freely variable setting of the signal delay time, so-called programmable delay operation, and thereby enable the time delay to occur fluidly in, for example, a system, circuit, or device. The present invention provides a signal processing technology that can reliably compensate for

The above and other objects and novel features of the present invention will become clear from the description of the present specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, by variably controlling the magnitude of the delay time caused by the delay element using a switching circuit, the amount of delay can be electrically programmed, thereby fluidly compensating for timing deviations that occur in, for example, digital logic circuits and achieving stability. This achieves the purpose of making it possible to ensure a stable operating state.

〔Example〕

Hereinafter, typical embodiments of the present invention will be described with reference to the drawings.

In the drawings, the same or corresponding parts are indicated by the same reference numerals.

FIG. 1 shows a programmable delay circuit which is an embodiment of the present invention.

The programmable delay circuit shown in the figure is formed together with a digital logic circuit in an MO8 type semiconductor integrated circuit device. A digital logic circuit is one in which a large number of logic elements are formed in advance, such as a master slice, and various logic circuits or systems can be constructed by connecting these logic elements as appropriate according to the user's order. be.

By the way, the programmable delay circuit 100, the embodiment of which will be shown below, can basically be configured with at least one delay element 10, but in the illustrated embodiment, the following combinations are used to 17 are used.

That is, the delay elements 10 are assembled in units of one or more, and each set unit is connected in series to form four delay element groups n in the embodiment.
, 2n, 4n, and 8n. Each delay element group n
, 2n, 4n, and 8n each function as if they were one delay element. These delay element groups n, 2n, 4n,
8n are connected in series, and each delay element group n, 2n.

Switching circuits 81.4n and 8n each bypass the input side and the output side. S2 and 83°S4 are connected.

Furthermore, the delay times of each delay element group n, 2n, 4n, and 8n are weighted to different degrees. In the embodiment, the first delay element group n counting from the input IN side
is the delay time of tdl by one delay element 10Vc,
The second delay element group 2n has a delay time of 2tdl with two delay elements 10, the third delay element group 4n has a delay time of 4tdl with four delay elements 10, and the output QUT side delay element group 8n The eight delay elements 10 each take charge of a delay time of 8 tdl. In other words, weighting is performed using a binary power number.

Each of the switching circuits 81, 82, 83, and 84 is configured to operate as a so-called selective switch by means of two switching elements to be described later. Depending on f'L, whether the delayed signal is passed through the delay element group or bypassed.

In other words, it is possible to select whether to keep or kill a delay element group for each delay element group. Each switching circuit 81. S2, 83° The operating state of S4 is controlled by externally applied control signals DI, D2. D3. It is electrically and individually set by D4. control signal DI,
D2. D3 and D4 are digital signals, for example, binary 4-bit control data whose contents can be changed depending on the design or operation status of the digital logic circuit. This causes the control signal DJ.

D2. D3. The delay time can be variably set in stages according to the contents of D4.

For example, as shown in FIG. 2, the control signal DI.

D2. D3. All delay element groups n by D4.

Bypassing 2n, 4n, and 8n, the input cuckold Pi
A pulse Po having the same timing as n is output.

In addition, a pulse P1 having a time delay of tdx with respect to the input cabling signal Pin is outputted so as to take advantage of the delay of the first delay element group n. Similarly, if only the second delay element group 2n is activated, the pulse P2 with a time delay a of 2td becomes -゛If only the third delay element group 4n is activated, the pulse P3 with a time delay a of 4td. Then, only the delay element group 8n on the output QUT side is utilized, and the output signal P4 with a time delay of 8td is output.
If only 0 is utilized, a pulse P34 with a time delay of 4td+8td-12td is output. Also, if all delay element groups n, 2n, 3n, 4n' are used, td+21
A pulse P1234 with a time delay of d+4td+8td=15td is now output. In this way, the control signals DI, D2 . D3. By combining D4, the delay time from 0 to 15td can be freely set in td increments, and in small increments over a wide range.

FIG. 3 shows an embodiment of the delay element 10 described above.

The delay element 10 shown in the figure corresponds to the first delay element group n in the delay circuit 100 in FIG.

The delay element 10 shown in FIG. 3 includes three sets of 0-MO8 field effect transistors Ql-Q2. It is constructed using Q3-Q4°Q5-Q6. Among them, two sets of 0-MO8 field effect transistors Ql-Q2°Q3-Q4 constitute innocutors II and I2 as logic circuits, respectively. The signal introduced at the input IN is connected to its two inverters II
, I2 are transmitted to the output QUT in positive logic. At this point, each inverter II.

The sum of the transmission delays occurring at I2 is the aforementioned delay time td.

The set of 0-MO8 field effect transistors Q5 and Q6 are respectively used as switching elements and constitute the switching circuit S1 described above. One MO3i field effect transistor Q5 connects the input IN and output QU of the delay element 10.
The on-resistance of this MO3 field effect transistor Q5 is sufficiently small.The other MO8 field effect transistor Q6 is interposed on the output side of the subsequent inverter I2. Both MO5iIE field effect transistors Q5 and Q6 are controlled to be conductive in a complementary manner by the control signal D1.That is, when one MO8 field effect transistor Q5 is turned on,
The other MO8 field effect transistor Q6 is turned off, and this transition delay element 10 is connected to its input IN side and output QU.
The T side is bypassed. Further, when one MO8 field effect transistor Q5 is turned off, the other MO8 field effect transistor Q6 is turned on, and the delayed signal is delayed through the delay element 10.

Note that vcc indicates a positive power supply potential.

In the manner described above, the programmable delay circuit 100 is configured in which the delay time can be freely and variably set electrically. This programmable delay circuit 100 can, for example, dynamically compensate for timing deviations that occur in a digital logic system, circuit, or device depending on the design or operating state, or can be used to compensate for timing deviations that occur within a digital logic system, circuit, or device, or in the case of a master slice, according to a user's order. It is suitable for applications such as forming a delay compensation circuit to enable assembled logic circuits to operate normally.

Further, as shown in FIG. 4, the output QUT of the programmable delay circuit 100 described above is
By performing NAND logic between I and the input IN, it is possible to configure a kind of waveform shaping circuit that can vary the width, so-called duty, of the pulse output to the AND output 0UT2.

FIG. 5 shows the waveform shaping operation. As shown in the figure, a pulse with a delay time tdx by the delay circuit 100 is obtained at 0UT1 with respect to the width τ of the pulse at the input IN, and a pulse whose width is longer by this delay time tdx is 0UUT1.
Obtained at T2. At this time, since the delay time taX can be freely programmed, the pulse width τ-t of 0UT2
DX module can be programmed with any 1C. Please note that NA
It goes without saying that waveform shaping may be performed by using an A N D circuit, a NOR circuit, etc. in addition to the N D circuit.

〔effect〕

(1) It consists of at least one delay element and a switching circuit that bypasses the input side and output side of this delay element, and the on/off state of the switching circuit is determined by a signal applied from the outside. By electrically setting the delay time, a delay circuit is constructed in which the delay time of a signal can be freely and variably set electrically, or so-called programmable delay operation can be performed. This provides the effect that it becomes possible to reliably compensate for time delays that occur dynamically in devices and the like.

(2) Furthermore, a plurality of the delay elements are connected in series,
The switching circuit f12 is connected between the input side and the output side of each delay element, and the delay time of each delay element is weighted with different magnitudes, thereby controlling the variable range of the delay time. The effect is that it can be performed in large and small steps.

Therefore, if used as a block cell of a gate array, a high-performance semiconductor integrated circuit device with a function of controlling delay time can be provided.

The invention made by the present inventor has been specifically explained above based on examples, but it goes without saying that this invention is not limited to the above examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the logic element may be constructed of a bipolar logic circuit.

[Application field]

The above explanation has mainly been about the case where the invention made by the present inventor is applied to signal processing technology in digital logic circuits, which is the background field of application, but the invention is not limited thereto. It can also be applied to signal processing technology, etc. It can be applied at least to conditions involving delay elements.

[Brief explanation of the drawing]

4 is a circuit diagram showing one embodiment of the programmable delay circuit according to the present invention, FIG. 2 is a waveform chart showing an example of the operation of the circuit shown in FIG. 1, and FIG. 3 is an example of the circuit shown in FIG. 1. 4 is a circuit diagram showing an example of application of the programmable delay circuit according to the present invention; and FIG. 5 is a waveform chart showing an example of the operation of the circuit shown in FIG. 4. 10... Delay element, n, 2n, 4n, 8n... Delay element group, Sl, S2, 83, 84... Switching circuit, DI, D2. D3. D4 knee control signal, 100
...Programmable delay circuit, Ql', Q2. Q
3゜Q4. Q5. 4O8 field effect transistor to Q6...11. , I2=・inverter, t d, tdx−
Delay time, VCC...constant potential, 20...AND circuit. Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] 1. Consisting of one delay element and a switching circuit that bypasses the input side and output side of this delay element, and furthermore, the switching circuit has an on/off state that is externally controlled. A programmable delay circuit characterized in that it is configured to be electrically set by a signal given from a programmable delay circuit. 2. The delay element is configured by connecting a predetermined number of logic circuits in series, and the delay element is configured by connecting a predetermined number of logic circuits in series. The programmable delay circuit according to claim 1, characterized in that a predetermined delay time is provided by a transmission delay. 3. A plurality of the delay elements are connected in series, and the input side of each delay element and The switching circuit is connected between the output sides, and the delay time of each delay element is weighted with different magnitudes. The programmable delay circuit according to paragraph 4. The switching circuit comprises two switching elements that operate complementary to each other, one of which is connected to form a bypass path between the input side and the output side of the delay element, The programmable device according to any one of claims 1 to 3, characterized in that the other is connected so as to separate the signal transmission path by the delay element. Delay circuit. 5. Consists of at least one delay element and a switching circuit that bypasses the input side and output side of this delay element, and furthermore, the switching circuit has an on/off state that can be changed from the outside. A semiconductor integrated circuit device comprising a delay time control circuit configured to be electrically set by an applied signal.