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JPS6481042A - Emergency restarting system - Google Patents

Emergency restarting system

Info

Publication number
JPS6481042A
JPS6481042A JP62237404A JP23740487A JPS6481042A JP S6481042 A JPS6481042 A JP S6481042A JP 62237404 A JP62237404 A JP 62237404A JP 23740487 A JP23740487 A JP 23740487A JP S6481042 A JPS6481042 A JP S6481042A
Authority
JP
Japan
Prior art keywords
restart
emergency
fault
circuits
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62237404A
Other languages
Japanese (ja)
Inventor
Yoshifumi Sasamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62237404A priority Critical patent/JPS6481042A/en
Publication of JPS6481042A publication Critical patent/JPS6481042A/en
Pending legal-status Critical Current

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  • Hardware Redundancy (AREA)

Abstract

PURPOSE:To enable a restart circuit to restart by itself despite the abnormality of the restart circuit by designating forcibly an emergency restart action from outside when a duplex processor has a fault. CONSTITUTION:A duplex processor consists of a 1st system P1 and a 2nd system P2 which contains the emergency restart circuits EM1 and EM2. When such a fault that disables both circuits EM1 and EM2 from their actuation is generated and the processing is stopped, this fact is detected by a supervisory equipment and signals EN, A and B are set at 1, 0 and 1 respectively. Then a forcible restart action is carried out based on the system formation logic of the processor itself. Then the signals EN, A and B set at 1, 1 and 0 and then 1, 1 and 1 are successively produced when the correct processing is not performed yet. Thus the system formation can be forcibly designated from outside.
JP62237404A 1987-09-24 1987-09-24 Emergency restarting system Pending JPS6481042A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62237404A JPS6481042A (en) 1987-09-24 1987-09-24 Emergency restarting system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62237404A JPS6481042A (en) 1987-09-24 1987-09-24 Emergency restarting system

Publications (1)

Publication Number Publication Date
JPS6481042A true JPS6481042A (en) 1989-03-27

Family

ID=17014888

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62237404A Pending JPS6481042A (en) 1987-09-24 1987-09-24 Emergency restarting system

Country Status (1)

Country Link
JP (1) JPS6481042A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4921815A (en) * 1972-06-28 1974-02-26
JPS6116340A (en) * 1984-07-03 1986-01-24 Nec Corp Emergency operation device of processor system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4921815A (en) * 1972-06-28 1974-02-26
JPS6116340A (en) * 1984-07-03 1986-01-24 Nec Corp Emergency operation device of processor system

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