JPS5453929U - - Google Patents
Info
- Publication number
- JPS5453929U JPS5453929U JP12626877U JP12626877U JPS5453929U JP S5453929 U JPS5453929 U JP S5453929U JP 12626877 U JP12626877 U JP 12626877U JP 12626877 U JP12626877 U JP 12626877U JP S5453929 U JPS5453929 U JP S5453929U
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12626877U JPS5453929U (en) | 1977-09-21 | 1977-09-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12626877U JPS5453929U (en) | 1977-09-21 | 1977-09-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5453929U true JPS5453929U (en) | 1979-04-14 |
Family
ID=29087937
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12626877U Pending JPS5453929U (en) | 1977-09-21 | 1977-09-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5453929U (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7116577B2 (en) | 1997-08-01 | 2006-10-03 | Saifun Semiconductors Ltd | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
| US7221138B2 (en) | 2005-09-27 | 2007-05-22 | Saifun Semiconductors Ltd | Method and apparatus for measuring charge pump output current |
| US7317633B2 (en) | 2004-07-06 | 2008-01-08 | Saifun Semiconductors Ltd | Protection of NROM devices from charge damage |
| US7352627B2 (en) | 2006-01-03 | 2008-04-01 | Saifon Semiconductors Ltd. | Method, system, and circuit for operating a non-volatile memory array |
| US7369440B2 (en) | 2005-01-19 | 2008-05-06 | Saifun Semiconductors Ltd. | Method, circuit and systems for erasing one or more non-volatile memory cells |
| US7420848B2 (en) | 2002-01-31 | 2008-09-02 | Saifun Semiconductors Ltd. | Method, system, and circuit for operating a non-volatile memory array |
| US7457183B2 (en) | 2003-09-16 | 2008-11-25 | Saifun Semiconductors Ltd. | Operating array cells with matched reference cells |
| US7466594B2 (en) | 2004-08-12 | 2008-12-16 | Saifun Semiconductors Ltd. | Dynamic matching of signal path and reference path for sensing |
| US7512009B2 (en) | 2001-04-05 | 2009-03-31 | Saifun Semiconductors Ltd. | Method for programming a reference cell |
| US7532529B2 (en) | 2004-03-29 | 2009-05-12 | Saifun Semiconductors Ltd. | Apparatus and methods for multi-level sensing in a memory array |
| US7605579B2 (en) | 2006-09-18 | 2009-10-20 | Saifun Semiconductors Ltd. | Measuring and controlling current consumption and output current of charge pumps |
| US7638850B2 (en) | 2004-10-14 | 2009-12-29 | Saifun Semiconductors Ltd. | Non-volatile memory structure and method of fabrication |
| US7638835B2 (en) | 2006-02-28 | 2009-12-29 | Saifun Semiconductors Ltd. | Double density NROM with nitride strips (DDNS) |
-
1977
- 1977-09-21 JP JP12626877U patent/JPS5453929U/ja active Pending
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7116577B2 (en) | 1997-08-01 | 2006-10-03 | Saifun Semiconductors Ltd | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
| US7405969B2 (en) | 1997-08-01 | 2008-07-29 | Saifun Semiconductors Ltd. | Non-volatile memory cell and non-volatile memory devices |
| US7512009B2 (en) | 2001-04-05 | 2009-03-31 | Saifun Semiconductors Ltd. | Method for programming a reference cell |
| US7420848B2 (en) | 2002-01-31 | 2008-09-02 | Saifun Semiconductors Ltd. | Method, system, and circuit for operating a non-volatile memory array |
| US7457183B2 (en) | 2003-09-16 | 2008-11-25 | Saifun Semiconductors Ltd. | Operating array cells with matched reference cells |
| US7532529B2 (en) | 2004-03-29 | 2009-05-12 | Saifun Semiconductors Ltd. | Apparatus and methods for multi-level sensing in a memory array |
| US7317633B2 (en) | 2004-07-06 | 2008-01-08 | Saifun Semiconductors Ltd | Protection of NROM devices from charge damage |
| US7466594B2 (en) | 2004-08-12 | 2008-12-16 | Saifun Semiconductors Ltd. | Dynamic matching of signal path and reference path for sensing |
| US7638850B2 (en) | 2004-10-14 | 2009-12-29 | Saifun Semiconductors Ltd. | Non-volatile memory structure and method of fabrication |
| US7468926B2 (en) | 2005-01-19 | 2008-12-23 | Saifun Semiconductors Ltd. | Partial erase verify |
| US7369440B2 (en) | 2005-01-19 | 2008-05-06 | Saifun Semiconductors Ltd. | Method, circuit and systems for erasing one or more non-volatile memory cells |
| US7221138B2 (en) | 2005-09-27 | 2007-05-22 | Saifun Semiconductors Ltd | Method and apparatus for measuring charge pump output current |
| US7352627B2 (en) | 2006-01-03 | 2008-04-01 | Saifon Semiconductors Ltd. | Method, system, and circuit for operating a non-volatile memory array |
| US7638835B2 (en) | 2006-02-28 | 2009-12-29 | Saifun Semiconductors Ltd. | Double density NROM with nitride strips (DDNS) |
| US7605579B2 (en) | 2006-09-18 | 2009-10-20 | Saifun Semiconductors Ltd. | Measuring and controlling current consumption and output current of charge pumps |