JPH069209B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a bipolar transistor semiconductor device having a flat electrode wiring surface on a semiconductor substrate.

[Conventional technology]

At present, all semiconductor devices, especially bipolar transistors, have a so-called planar structure. In manufacturing this, the collector extraction part was first opened in the epitaxial layer on the semiconductor substrate to form a high impurity concentration region. It is usual to add a post-thermal oxidation step to temporarily close this opening with a thermal oxide film of silicon and then move to the step of forming the next base region and emitter region. As is well known, the high-concentration impurity region functions to reduce the resistance of the collector region and is a high-concentration impurity diffusion layer extending to a depth reaching the buried layer formed on the connection surface between the semiconductor substrate and the epitaxial layer. .

[Problems to be solved by the invention]

However, according to this conventional manufacturing method, when the thermal oxide film of silicon that closes the opening is finally removed to form the collector electrode, this oxide film originally consists of the thermal oxide film of the epitaxial layer, and thus the opening Therefore, after forming the electrode wiring, only the collector electrode wiring is formed one step lower than the base and emitter electrode wirings to form an electrode wiring surface having an extremely uneven height. If a deep step is formed in the collector extraction opening in this way, the coverage of the aluminum electrode wiring is deteriorated, which causes a disconnection accident, so that the reliability and manufacturing yield of the transistor device are greatly reduced. Conventionally, various measures have been taken to eliminate the vertical step of the collector extraction opening, for example, a method of forming a tapered edge long by using isotropic etching when opening the opening, or a method of forming an interlayer insulating film A method of reducing the film thickness to reduce the etching step is performed. However, the former method improves the coverage of the electrode wiring but cannot increase the degree of integration. The latter method does not prevent high integration, but pinholes frequently occur in the inter-layer insulation film for insulation. There is a problem with the breakdown voltage and the manufacturing yield is reduced.

In view of the above situation, it is an object of the present invention to provide a method for manufacturing a semiconductor device without forming a step in the extraction opening of the collector.

[Means for solving problems]

A method for manufacturing a semiconductor device of the present invention comprises a step of sequentially forming a buried layer of an opposite conductivity type and an epitaxial layer on a semiconductor substrate of one conductivity type, and a step of forming an element isolation region in the epitaxial layer, A step of forming a first silicon oxide film on an epitaxial layer surrounded by the element isolation region; a step of forming a collector take-out opening for selectively etching the first silicon oxide film; A high-concentration impurity-added region forming step of diffusing a high-concentration impurity of opposite conductivity type to a depth reaching the buried layer and an etch-back method of etching a second silicon oxide film in the step of the collector extraction opening are used. And then burying.

That is, according to the present invention, the collector extraction opening formed in the epitaxial layer is selectively filled with a new silicon oxide film and flattened after a high concentration of impurities is diffused.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to the drawings.

1A to 1D are process sequence diagrams showing an embodiment of the present invention. According to the present embodiment, as shown in FIG. 1A, the n-type buried layer 2 and the n-type epitaxial layer 3 are first formed on the p-type semiconductor substrate 1, and then the p-type high concentration impurity region 4 is formed. The pressure film element isolation region 5 is formed by a known technique. Here, a collector extraction opening is formed on the silicon oxide film 6 covering the element formation region surrounded by the pressure film element isolation region 5 by using the silicon nitride film 7 as a mask, and the n-type high concentration impurity added region is formed. After 8 is formed, a silicon oxide film 9 by vapor deposition and a liquid coating film 10 of a photoresist material or silica are sequentially formed on the entire surface of the substrate. At this time, since the liquid coating film 10 fills the level difference in the collector extraction opening, the entire substrate is smoothed.
Here, the entire surface of the substrate is etched by the etch back method. The thin silicon oxide film 9 on the thick film element isolation region 5 and the silicon oxide film 6 formed by the vapor phase growth process and the liquid coating film 10 applied thereon are removed together with the silicon nitride film 7 by this etching process. As a result, the silicon oxide film 9 by vapor phase growth is left only in the step of the collector extraction opening. FIG. 1 (b) shows this state.

Thus, the state in which the collector extraction opening is filled with the silicon oxide film 9 by vapor phase growth is different from the case where the conventional thermal oxide film of the n-type epitaxial layer 3 is filled.
The feature is that no bite into the n-type high-concentration impurity added region 8 occurs. Therefore, as shown in FIG. 1C, the base region 11 and the emitter region 12 are formed according to the conventional technique.
Then, the silicon oxide film 9 is removed and the collector and emitter extraction electrodes 13 and 14 are formed by patterning polycrystalline silicon, so that the heights of the two polycrystalline silicon electrodes 13 and 14 are made uniform. be able to. That is, the extraction electrode can be formed without forming a step in the collector extraction opening. Thereafter, the interlayer insulating film 15 is covered and the collector, emitter, and base aluminum electrodes 16, 17 and 18 are formed, respectively, to complete the semiconductor device of the present invention as shown in FIG. 1 (d). As is apparent from FIG. 1 (d), in the semiconductor device of the present invention, the collector take-out opening has no level difference as in the prior art, and the surface where each electrode wiring is formed is flattened. Not only the parts but also the coverage characteristics of all the aluminum electrodes can be remarkably improved, and the reliability and the manufacturing yield can be remarkably improved.

FIG. 2 is a partial process drawing showing another embodiment of the present invention.
According to this embodiment, the n-type high-concentration impurity doped region 8 is formed in the collector extraction opening, and then the polycrystalline silicon layer 19 is deposited on the entire surface of the substrate. Here, the polycrystalline silicon layer 19 is immediately thermally oxidized and converted into a silicon oxide layer, and then etched back as in the previous embodiment. Most of the silicon oxide layer converted by this etch-back process is removed and left so as to be buried only in the step of the collector extraction opening. That is, the state is exactly the same as in FIG. Therefore, after that, if the steps of the same procedure as in the previous embodiment are performed, the structure of the semiconductor device of the present invention shown in FIG. 1D can be obtained. Although the NPN transistor has been described above, it is clear that the same effect can be produced in the manufacture of the PNP transistor.

Further, although the step of the collector extraction opening is filled with the silicon oxide film by the selective removing means in the above, it is of course possible to fill the step by the selective depositing means.

〔The invention's effect〕

As described above in detail, according to the present invention, the collector extraction opening, which has been subjected to the impurity diffusion without thermally oxidizing the epitaxial layer, can be closed with the silicon oxide film. It is possible to completely solve the step problem due to the bite into the area. That is, the coverage characteristics in the collector extraction opening can be significantly improved to improve reliability and manufacturing yield, and the surface where the electrode wiring of each transistor is formed can be flattened. Can play.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 (a) to (d) are process flow charts showing an embodiment of the present invention, and FIG. 2 is a partial process chart showing another embodiment of the present invention. 1 ... p-type semiconductor substrate, 2 ... n-type buried layer, 3 ... n-type epitaxial layer, 4 ... p-type high-concentration impurity region, 5 ... thick film element isolation region, 6 ... silicon oxide film, 7 ... silicon nitride film, 8 ... N-type high-concentration impurity added region, 9 ... Vapor phase grown silicon oxide film, 10 ... Liquid coating film, 11 ... Base region, 12 ... Emitter region, 13 ... (Polycrystalline silicon) collector extraction electrode, 14 ... Emitter extraction electrode (made of polycrystalline silicon), 15 ... Interlayer insulating film, 16 ... Collector aluminum electrode, 17 ... Emitter aluminum electrode, 18
... base / aluminum electrode, 19 ... polycrystalline silicon layer.

Claims (1)

[Claims] 1. A step of sequentially forming a buried layer and an epitaxial layer of opposite conductivity type on a semiconductor substrate of one conductivity type,
Forming an element isolation region in the epitaxial layer; forming a first silicon oxide film on the epitaxial layer surrounded by the element isolation region; and a collector for selectively etching the first silicon oxide film. A step of forming an extraction opening, a step of forming a high-concentration impurity doped region for diffusing a high-concentration impurity of opposite conductivity type to a depth reaching the buried layer from the collector extraction opening, and a step of the collector extraction opening. And a step of burying a second silicon oxide film by using an etch back method.