JP4756080B2 - Method for manufacturing nonvolatile memory device - Google Patents

Description

  The present invention relates to a method for manufacturing a nonvolatile memory device.

  A flash memory frequently used as a non-volatile storage device is considered to have a limit for improving the degree of integration. As a non-volatile memory device capable of higher integration than a flash memory, for example, a cross-point type non-volatile memory device having a configuration in which a memory layer (memory unit) having a variable electric resistance is sandwiched between two electrodes has attracted attention. (For example, patent document 1). There is also a non-volatile memory device having a three-dimensional structure in which the cross-point type non-volatile memory devices are stacked.

  In manufacturing such a cross-point type nonvolatile memory device, for example, a memory layer to be a memory cell is processed into a shape corresponding to a bit line, an interlayer insulating film is embedded between them, and then a word line is formed thereon. A word line is formed by dry etching using, for example, a silicon oxide film formed by laminating a plurality of metal films and processed into a shape corresponding to the word line by photolithography.

  At this time, when the memory layer is processed, the lower part of the memory layer may have a taper having a larger area than the upper part. If an interlayer insulating film is embedded between the memory layers in this state, the interlayer insulating film and At the interface with the memory layer, the interlayer insulating film covers the memory layer. In this state, if the processing for forming the word lines is performed, a memory layer that is not processed by the shadow of the interlayer insulating film remains between the word lines on the bit lines, causing a short circuit between the word lines. was there.

JP 2007-184419 A

  The present invention provides a method for manufacturing a high-yield nonvolatile memory device in which processing defects in a memory portion between wirings are reduced.

  According to one aspect of the present invention, a plurality of first electrodes extending in a first direction and a second direction that is non-parallel to the first direction are provided on the first electrode. A plurality of second electrodes, and a first memory layer provided between the first electrode and the second electrode, the resistance of which varies according to at least one of an applied electric field and an energized current. A non-volatile memory device manufacturing method having a memory unit, comprising: a first electrode film serving as a first electrode; and a first memory film serving as a first memory unit on a main surface of a substrate. A step of laminating, a step of processing the first electrode film and the first memory film into a strip extending in a first direction, and the processed first electrode film and the first memory film And a step of embedding a sacrificial layer between the first memory portion film and the sacrificial layer, a second electrode film serving as a second electrode Forming a mask layer having a slower etching rate than the sacrificial layer on the second electrode film, and extending the second electrode film in the second direction using the mask layer as a mask. A step of processing into a strip shape, using the mask layer as a mask, removing a portion of the first memory portion film exposed from the sacrificial layer, and removing the first memory portion film from the side wall along the first direction; Processing into a columnar shape having sidewalls along the second direction, removing the sacrificial layer to expose the first memory film covered by the sacrificial layer, and exposing the exposed first There is provided a method for manufacturing a non-volatile memory device, comprising the step of removing one memory portion film.

  According to another aspect of the present invention, a plurality of first electrodes extending in a first direction, and extending in a second direction non-parallel to the first direction and provided on the first electrode A plurality of second electrodes, a plurality of third electrodes extending in a third direction non-parallel to the second direction and provided on the second electrode, the first electrode, A first memory unit provided between the second electrode and having a first memory layer whose resistance changes according to at least one of an applied electric field and an energized current; the second electrode; and the third electrode; A non-volatile memory device having a second memory layer having a second memory layer, the resistance of which varies between at least one of an applied electric field and an energized current, On the main surface of the first electrode film, a first electrode film serving as a first electrode, and a first memory section film serving as a first memory section , A step of processing the first electrode film and the first memory portion film into a strip shape extending in a first direction, the processed first electrode film and the first memory portion A step of embedding a sacrificial layer between the films, a second electrode film serving as a second electrode on the first memory unit film and the sacrificial layer, a second memory unit film serving as a second memory unit, A step of forming a mask layer having an etching rate slower than that of the sacrificial layer on the second memory portion film, and the second electrode film and the second memory using the mask layer as a mask. A step of processing the part film into a strip extending in the second direction, and using the mask layer as a mask, a portion exposed from the sacrificial layer of the first memory part film is removed, and the first memory part film A columnar shape having a side wall along the first direction and a side wall along the second direction And removing the sacrificial layer to expose the first memory portion film covered with the sacrificial layer, and removing the exposed first memory portion film. A non-volatile memory device manufacturing method is provided.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the high yield non-volatile memory device which reduced the processing defect of the memory | storage part between wiring is provided.

FIG. 4 is a flowchart illustrating the method for manufacturing the nonvolatile memory device according to the first embodiment of the invention. 1 is a schematic view illustrating the configuration of a nonvolatile memory device manufactured by a method of manufacturing a nonvolatile memory device according to a first embodiment of the invention. 1 is a schematic cross-sectional view illustrating the configuration of a nonvolatile memory device manufactured by a method for manufacturing a nonvolatile memory device according to a first embodiment of the invention. FIG. 6 is a schematic cross-sectional view in order of the processes, illustrating the method for manufacturing the nonvolatile memory device according to the first embodiment of the invention. FIG. 5 is a schematic cross-sectional view in order of the steps, following FIG. 4. FIG. 6 is a schematic cross-sectional view in order of the steps, following FIG. 5. FIG. 7 is a schematic cross-sectional view in order of the steps, following FIG. 6. FIG. 8 is a schematic cross-sectional view in order of the steps, following FIG. 7. FIG. 9 is a schematic cross-sectional view in order of the steps, following FIG. 8. FIG. 10 is a schematic cross-sectional view in order of the steps, following FIG. 9. 7 is a schematic cross-sectional view in order of the processes, illustrating a method for manufacturing a nonvolatile memory device according to a comparative example. FIG. 12 is a schematic cross-sectional view in order of the steps, following FIG. 11. FIG. 13 is a schematic cross-sectional view in order of the steps, following FIG. 12. FIG. 6 is a flowchart illustrating a method for manufacturing a nonvolatile memory device according to a second embodiment of the invention. FIG. 6 is a schematic view illustrating the configuration of a nonvolatile memory device manufactured by a method for manufacturing a nonvolatile memory device according to a second embodiment of the invention. FIG. 6 is a schematic cross-sectional view illustrating the configuration of a nonvolatile memory device manufactured by a method for manufacturing a nonvolatile memory device according to a second embodiment of the invention. FIG. 5D is a schematic cross-sectional view in order of the process, illustrating a method for manufacturing a nonvolatile memory device according to a second embodiment of the invention. FIG. 18 is a schematic cross-sectional view in order of the steps, following FIG. 17. FIG. 6 is a schematic perspective view illustrating the configuration of another nonvolatile memory device manufactured by the method for manufacturing a nonvolatile memory device according to the second embodiment of the invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
Note that, in the present specification and each drawing, the same elements as those described above with reference to the previous drawings are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.

(First embodiment)
FIG. 1 is a flowchart illustrating the method for manufacturing the nonvolatile memory device according to the first embodiment of the invention.
FIG. 2 is a schematic view illustrating the configuration of the nonvolatile memory device manufactured by the nonvolatile memory device manufacturing method according to the first embodiment of the invention.
2A is a perspective view, and FIG. 2B is a plan view.
FIG. 3 is a schematic cross-sectional view illustrating the configuration of the nonvolatile memory device manufactured by the nonvolatile memory device manufacturing method according to the first embodiment of the invention.
3A is a cross-sectional view taken along the line AA ′ of FIG. 2B, FIG. 3B is a cross-sectional view taken along the line BB ′ of FIG. 2B, and FIG. It is CC 'sectional drawing of FIG.2 (b), FIG.3 (d) is DD' sectional drawing of FIG.2 (b).

FIG. 4 is a schematic cross-sectional view in order of the processes, illustrating the method for manufacturing the nonvolatile memory device according to the first embodiment of the invention.
FIG. 5 is a schematic cross-sectional view in order of the processes following FIG.
FIG. 6 is a schematic cross-sectional view in order of the processes following FIG.
FIG. 7 is a schematic cross-sectional view in order of the processes following FIG.
FIG. 8 is a schematic cross-sectional view in order of the processes following FIG.
FIG. 9 is a schematic cross-sectional view in order of the processes following FIG.
FIG. 10 is a schematic cross-sectional view in order of the processes following FIG.
4A to 10B, FIG. 4A is a cross-sectional view corresponding to line AA ′ in FIG. 2B, and FIG. 4B is a cross-sectional view taken along line BB in FIG. FIG. 2C is a cross-sectional view corresponding to line CC 'in FIG. 2B, and FIG. 2A is a cross-sectional view corresponding to line DD in FIG. 2B. It is sectional drawing corresponding to a line.

First, a nonvolatile memory device manufactured by the method for manufacturing a nonvolatile memory device according to the first embodiment of the present invention will be described with reference to FIGS.
As illustrated in FIGS. 2 and 3, the nonvolatile memory device 10 manufactured by the method of manufacturing a nonvolatile memory device according to this embodiment includes a plurality of first electrodes 110 extending in a first direction, Extending in a second direction non-parallel to one direction, provided between the plurality of second electrodes 140 provided on the first electrode 110, and between the first electrode 110 and the second electrode 140, And a first memory unit 130 having a first memory layer 132 whose resistance is changed by at least one of an applied electric field and an energized current. For example, the first electrode 110 is provided on the main surface 106 of the substrate 105.

  The first direction and the second direction are not parallel to each other and, for example, intersect three-dimensionally. Hereinafter, the case where the first direction and the second direction are orthogonal to each other will be described.

  Here, the first direction is the X-axis direction, and the second direction is the Y-axis direction orthogonal to the X-axis direction. A direction orthogonal to the X-axis direction and the Y-axis direction is taken as a Z-axis direction. The main surface 106 of the substrate 105 is perpendicular to the Z-axis direction and parallel to the XY plane. The first electrode 110 extends in a strip shape in the X-axis direction within a plane parallel to the XY plane. The second electrode 140 extends in a band shape in the Y-axis direction within a plane parallel to the XY plane.

  The first memory unit 130 is provided between the first electrode 110 and the second electrode 140 where the first electrode 110 and the second electrode 140 intersect three-dimensionally, and this becomes the first memory cell 135. . That is, the nonvolatile memory device 10 is a cross-point nonvolatile memory device using a resistance change film.

  For example, the first electrode 110 is a bit line, and the second electrode 140 is a word line. However, in the present invention, the first electrode 110 and the second electrode 140 can be interchanged, and the first electrode 110 may be a word line and the second electrode 140 may be a bit line.

  The first storage unit 130 includes a first storage layer 132. The first memory layer 132 is a layer whose resistance is changed by at least one of an applied electric field and an energized current. The first memory layer 132 has a resistance change material and a resistance change according to a phase change. For example, a phase change material can be used. Further, the first memory layer 132 may be formed by laminating various conductive films and various barrier films on a resistance change material layer or a phase change material layer.

For example, the first storage layer 132 includes NiO _x , TiO _x , CoO _x , TaO _x , MnO _x , WO _x , Al ₂ O ₃ , FeO _x , HfO _x , ZnMn ₂ O ₄ , ZnFe ₂ O ₄ , ZnCo _{2 O 4, ZnCr 2 O 4} , ZnAl 2 O 4, CuCoO 2, CuAlO 2, NiWO 4, NiTiO 3, CoAl 2 O 4, MnAl 2 O 4, ZnNiTiO 4, _and, like Pr _{x Ca 1-x} MnO ₃ Can be used.
In addition, the first memory layer 132 may be obtained by adding a dopant to the above-described various compounds.
However, the present invention is not limited to the above, and the material used for the first memory layer 132 is arbitrary.

  The first storage unit 130 can further include a first rectifying element 131 such as a diode. In this specific example, the first rectifying element 131 is provided between the first electrode 110 and the first memory layer 132, but the first rectifying element 131 includes the second electrode 140, the first memory layer 132, and the like. It may be provided between. As the first rectifying element 131, an element having various rectifying functions such as a PIN diode and a Schottky diode can be used. As the first rectifying element 131, a device in which an element having a rectifying function and various conductive films and various barrier films are stacked can be used.

  As described above, in the nonvolatile memory device 10, the first electrode 110, the first memory unit 130, and the second electrode 140 are stacked in the Z-axis direction and have a single-layer memory cell array (first memory cell array 101). is doing. However, the nonvolatile memory device manufactured by the method for manufacturing a nonvolatile memory device according to the embodiment of the present invention may have a configuration in which a plurality of memory cell arrays are stacked in the Z-axis direction. In the following, first, for the sake of simplicity, the case where the nonvolatile memory device 10 has a single-layer memory cell array will be described.

  As shown in FIGS. 3A to 3D, the first memory cell 135 formed between the first electrode 110 and the second electrode 140 is surrounded by a first oxide made of silicon oxide or the like. An interlayer insulating film 180 is embedded.

  Further, as will be described later, the first storage unit 130 may be tapered when the first storage unit 130 (the first rectifying element 131 and the first storage layer 132) is processed. Specifically, the cross-sectional area when the first storage unit 130 is cut along a plane parallel to the XY plane is large on the lower side (the substrate 105 side) and on the upper side (the side opposite to the substrate 105). The shape may become smaller.

  In the specification and drawings of the present application, for the sake of explanation, the taper of the first storage unit 130 is highlighted and described.

  In the method for manufacturing the nonvolatile memory device according to the present embodiment, processing defects do not occur even when the first memory unit 130 has a tapered shape.

  Hereinafter, a method for manufacturing the nonvolatile memory device according to the present embodiment will be described with reference to FIGS. 1 and 4 to 10.

First, as illustrated in FIG. 4, the first electrode film 110 f to be the first electrode 110 and the first memory film 130 f to be the first memory section 130 are stacked on the main surface 106 of the substrate 105. To do. Specifically, the first memory portion film 130 f is a stacked film of a first rectifying element film 131 f that becomes the first rectifying element 131 and a first memory layer film 132 f that becomes the first memory layer 132.
This process corresponds to step S110 illustrated in FIG.

Then, as illustrated in FIG. 4, the first electrode film 110 f and the first memory portion film 130 f are processed into a strip shape extending in the first direction (for example, the X-axis direction). Here, the first direction is the X-axis direction.
This process corresponds to step S120 illustrated in FIG.

  That is, the first electrode film is formed by, for example, RIE (Reactive Ion Etching) using a silicon oxide film mask (not shown) processed into a strip shape in the first direction in which the first electrode 110 extends by photolithography. 110f and the first memory film 130f are processed.

  At this time, as shown in FIG. 4, the first memory portion film 130 f may be processed into a tapered shape.

  That is, by processing the first electrode film 110f and the first memory film 130f into a band shape extending in the first direction, the width of the band on the first electrode film 110f side of the first memory film 130f (that is, the first memory film 130f) , The length in the direction perpendicular to the first direction) is longer than the width of the band on the side opposite to the first electrode film 110f (that is, the length in the direction perpendicular to the first direction). .

Then, as shown in FIG. 5, a sacrificial layer 181 is embedded between the processed first electrode film 110f and the first memory portion film 130f.
This process corresponds to step S130 illustrated in FIG.

  In this specific example, the sacrificial layer 181 is made of a novolac resin that is an organic film. That is, a novolac resin is applied on the first electrode film 110f, the first memory portion film 130f, and the substrate 105, and the novolac resin is embedded between the first electrode film 110f and the first memory portion film 130f, and the novolak resin is subjected to heat treatment. The resin is cured.

  Thereafter, for example, etching back is performed using a plasma containing ammonia and oxygen to reduce the thickness of the novolac resin. Thereafter, a first cap layer 182 (cap layer) made of, for example, silicon oxide is embedded by plasma CVD (Chemical Vapor Deposition) or a coating method, and planarized by CMP (Chemical Mechanical Polishing).

As a result, a structure in which the sacrificial layer 181 is disposed below the interface to be planarized by CMP and the first cap layer 182 is laminated thereon can be formed, and the sacrificial layer 181 is formed by the subsequent processing. Suppress unintended damage. Note that the thickness of the first cap layer 182 made of silicon oxide is desirably thin as long as damage to the sacrificial layer 181 is suppressed.
The first cap layer 182 may be provided as necessary and may be omitted.

After that, as illustrated in FIG. 6, the second electrode film 140 f to be the second electrode 140 is formed on the first electrode film 110 f, the first memory portion film 130 f, and the sacrificial layer 181 (and the first cap layer). To do.
This process corresponds to step S140 illustrated in FIG.

Then, as shown in FIG. 7, a mask layer 150 processed into the shape of the second electrode 140 is formed by photolithography.
This process corresponds to step S150 illustrated in FIG.

  The mask layer 150 has an etching rate slower than that of the sacrificial layer 181. For example, when a novolac resin is used as the sacrificial layer 181, silicon oxide is used for the mask layer 150.

Then, using the mask layer 150 as a mask, the second electrode film 140f is processed into a strip shape extending in the second direction. For this processing, for example, RIE is used.
This process corresponds to step S160 illustrated in FIG.

Thereafter, using the mask layer 150 as a mask, the first cap layer 182 made of silicon oxide is removed by dry etching or dilute hydrofluoric acid treatment.
As already described, the first cap layer 182 is provided as necessary, and this step is omitted when the first cap layer 182 is not formed. In addition, when the first cap layer 182 is thin, the step of removing the first cap layer 182 is not particularly provided, and the first cap layer 182 may be removed during other processing in a step described later.

Then, as illustrated in FIG. 8, using the mask layer 150 as a mask, a portion of the first memory portion film 130 f exposed from the sacrificial layer 181 is processed into a columnar shape. This columnar shape is a shape having a side wall along the first direction (X-axis direction) and a side wall along the second direction (Y-axis direction).
This process corresponds to step S170 illustrated in FIG.

  That is, in step S120 already described, the first memory film 130f is processed into a strip shape having side walls along the first direction (X-axis direction). Therefore, in step S170, the first memory film 130f is By processing so as to have a side wall along the second direction (Y-axis direction), it is processed into a columnar shape.

  In this specific example, the case where the side wall along the second direction of the first memory portion film 130f also has a tapered shape is illustrated.

  At this time, as illustrated in FIG. 8C, in the cross section taken along the line CC ′ of FIG. 2B, the first memory portion film 130f has a tapered shape, and the first memory in the portion is formed. Since the partial film 130f is covered with the sacrificial layer 181, the portion where the first memory film 130f is covered with the sacrificial layer 181 remains without being etched.

Then, as illustrated in FIG. 9, the sacrificial layer 181 is removed to expose the first memory portion film 130 f covered with the sacrificial layer 181.
This process corresponds to step S171 illustrated in FIG.

  When a novolac resin is used as the sacrificial layer 181, the sacrificial layer 181 can be removed using plasma using oxygen gas or a mixed gas of oxygen and ammonia, for example.

  At this time, as the sacrificial layer 181, for example, a novolac resin having an etching rate faster than that of the mask layer 150 (eg, silicon oxide) is used, so that the sacrificial layer 181 is formed without substantially damaging the mask layer 150. Can be removed.

Then, as illustrated in FIG. 10, the exposed first memory portion film 130 f is removed.
This process corresponds to step S172 illustrated in FIG.

  Then, for example, the mask layer 150 is removed, and the sacrificial layer 181 is removed by isotropic etching with plasma containing, for example, oxygen, ammonia, hydrogen, water, etc., and then the first electrode film 110f, between the first memory portion film 130f and the second electrode film 140f, silicon oxide to be the first interlayer insulating film 180 is embedded by a technique such as CVD or SOG (Spin On Glass), for example. The nonvolatile memory device 10 illustrated in FIG. 3 can be formed.

  In the above description, the sacrificial layer 181 is removed after step S172, and then the first interlayer insulating film 180 is formed. However, the sacrificial layer 181 is not removed after step S172, and the sacrificial layer 181 is left. The first interlayer insulating film 180 may be formed.

(Comparative example)
FIG. 11 is a schematic cross-sectional view in order of the processes, illustrating the method for manufacturing the nonvolatile memory device according to the comparative example.
FIG. 12 is a schematic cross-sectional view in order of the processes following FIG.
FIG. 13 is a schematic cross-sectional view in order of the processes following FIG.
11 is a diagram compared with FIG. 7 according to the present embodiment, FIG. 12 is a diagram compared with FIG. 8 according to the present embodiment, and FIG. 13 is a diagram according to the present embodiment. FIG.

  As shown in FIG. 11, in the method for manufacturing the nonvolatile memory device of the comparative example, the first electrode film 110f and the first memory film 130f are stacked on the substrate 105 (step S110), and the first electrode film is formed. 110f and the first memory portion film 130f are processed into a strip shape extending in the first direction (step S120), and thereafter, silicon oxide is formed between the first electrode film 110f and the first memory portion film 130f. An interlayer insulating film 190 is embedded.

  Then, a second electrode film 140f to be the second electrode 140 is formed (step S140), a mask layer 150 is formed (step S150), and the second electrode film 140f is extended in the second direction using the mask layer 150 as a mask. The existing belt is processed (step S160). The same silicon oxide as the interlayer insulating film 190 is also used for the mask layer 150.

  That is, in the manufacturing method according to the present embodiment, in step S130, the sacrificial layer 181 (for example, novolac resin) whose etching rate is faster than that of the mask layer 150 (for example, silicon oxide) is the first electrode film 110f and the first memory. In the manufacturing method of the comparative example, an interlayer insulating film 190 (for example, silicon oxide) having the same etching rate as that of the mask layer 150 is used.

  In the case of the comparative example, as shown in FIG. 12, the portion exposed from the interlayer insulating film 190 of the first memory portion film 130f is processed into a columnar shape (step S171), and as shown in FIG. When the interlayer insulating film 190 is to be removed, the etching selectivity between the interlayer insulating film 190 and the mask layer 150 cannot be obtained. Therefore, the thickness of the mask layer 150 is reduced by the etching for removing the interlayer insulating film 190. getting thin. Further, the line width of the mask layer 150 is reduced.

  That is, for example, if the interlayer insulating film 190 (silicon oxide film) is to be removed by dry etching, the amount of film reduction of the mask layer 150 (silicon oxide film) is significant, which is insufficient as a mask for subsequent dry etching. When the interlayer insulating film 190 is removed by dry etching, if the selection ratio between the interlayer insulating film 190 and the first electrode film 110f is not sufficient, the wiring portion of the first electrode film 110f, particularly the first electrode film 110f. As a result, the wiring lead-out portion is etched, and there is a problem of increase in wiring resistance or disconnection.

  On the other hand, when the interlayer insulating film 190 is removed using a chemical solution such as dilute hydrofluoric acid, the mask dimension is reduced by the receding of the mask layer 150 in the lateral direction because the etching is isotropic. In addition, since the silicon oxide film under the lead line portion for contact at the end of the wiring is also removed, there is no support below the lead line portion, so it collapses due to surface tension when the chemical solution is dried A problem occurs.

  As described above, in the comparative example, the mask layer 150 is damaged in the step of removing the interlayer insulating film 190.

  In the case of the comparative example, if the shape of the mask layer 150 is maintained to some extent, the removal of the interlayer insulating film 190 becomes incomplete.

  For this reason, as shown in FIG. 13C, the first memory portion film 130 f covered with the remaining interlayer insulating film 190 remains without being removed in the subsequent process, for example, the second electrode 140. This causes a short circuit between the two.

  On the other hand, in the method for manufacturing the nonvolatile memory device according to this embodiment, the sacrificial layer 181 made of a material whose etching rate is relatively faster than that of the mask layer 150 is used. Damage to the mask layer 150 is suppressed, and the sacrificial layer 181 covering the first memory portion film 130f in the region exposed from the mask layer 150 can be substantially completely removed. As a result, even when the first memory portion film 130f is processed into a tapered shape and the tapered portion of the first memory portion film 130f is covered with the sacrificial layer 181, the sacrificial layer 181 is completely removed, The first memory portion film 130f is exposed, and the first memory portion film 130f remaining in the shadow of the sacrificial layer 181 can be removed. And the problem of wiring resistance and disconnection in the wiring part of the first electrode film 110f can be avoided.

  Thus, according to the method for manufacturing a nonvolatile memory device according to the present embodiment, a method for manufacturing a nonvolatile memory device with a high yield in which processing defects in the memory unit between the wirings are reduced is provided.

  In the above description, in order to make the explanation of the effect of the present embodiment easier to understand, the case where the first memory portion film 130f has a tapered shape has been described. However, the side wall of the first memory portion film 130f has an XY plane. Even when the manufacturing method according to this embodiment is used, the manufacturing process margin can be expanded even when the manufacturing method according to this embodiment is substantially vertical. Can be improved.

  In the method for manufacturing the nonvolatile memory device according to this embodiment, the mask layer 150 and the sacrificial layer 181 need only have an etching rate slower than that of the sacrificial layer 181.

  For example, when an organic film such as an epoxy resin such as a novolac resin or an acrylic resin is used for the sacrificial layer 181, the mask layer 150 is selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide. At least one of them can be used.

  In the case where a coating-type solution is used as the sacrificial layer 181, it is desirable to use a material with low surface tension and high wettability. Thereby, it can apply | coat with wettability between the processed 1st electrode film 110f and the 1st memory | storage part film | membrane 130f, and generation | occurrence | production of a void etc. can be suppressed.

  For example, when silicon oxide is used for the sacrificial layer 181, the mask layer 150 can use, for example, at least one of silicon nitride and silicon carbide.

  As already described, after step S130 (embedding of the sacrificial layer 181 between the processed first electrode film 110f and the first memory portion film 130f), the processed first electrode film 110f and the first electrode film 110f are processed. By burying the first cap layer 182 (for example, a film made of silicon oxide) whose etching rate is slower than that of the sacrificial layer 181 between the one memory portion films 130f, damage to the sacrificial layer 181 can be suppressed.

Further, in the step of removing the sacrificial layer 181 in step S171, when an organic material is used for the sacrificial layer 181, at least one of the group consisting of O ₂ , H ₂ , H ₂ O, NH ₃ and CH ₄ is used. A treatment using a plasma containing a gas having the following can be employed. Accordingly, the sacrificial layer 181 made of an organic material can be etched without requiring large ion energy, the retreat amount of the mask layer 150 can be reduced, and the margin of the processing process can be expanded.

  For removal of the sacrificial layer 181 in step S171, for example, isotropic etching using downflow plasma using microwaves may be used, and anisotropic etching using RIE, for example, may be used. It may be used.

  At this time, if the sacrificial layer 181 is isotropically etched, the sacrificial layer 181 located under the second electrode 140 (mask layer 150) is also etched, but if the sacrificial layer 181 is anisotropically etched, The sacrificial layer 181 located under the two electrodes 140 (mask layer 150) is not completely removed.

  In the process of removing the sacrificial layer 181, when plasma containing a large amount of oxygen is used, the first electrode 110 and the second electrode 140 are easily oxidized materials such as tungsten, or the first memory layer 132 is formed. If the characteristics are likely to change due to oxidation, a silicon oxide film, a silicon nitride film, or the like is formed on the sidewalls of the first electrode film 110f, the second electrode film 140f, and the first memory portion film 130f by an ALD (Atomic Layer Deposition) method or the like. By forming the protective film, oxidation and reaction of the sidewall can be suppressed.

(Second Embodiment)
The method for manufacturing a nonvolatile memory device according to the second embodiment of the present invention is applied to a nonvolatile memory device in which a plurality of memory cell arrays are stacked.

FIG. 14 is a flowchart illustrating the method for manufacturing the nonvolatile memory device according to the second embodiment of the invention.
FIG. 15 is a schematic view illustrating the configuration of a nonvolatile memory device manufactured by the method for manufacturing a nonvolatile memory device according to the second embodiment of the invention.
15A is a perspective view, and FIG. 15B is a plan view.
FIG. 16 is a schematic cross-sectional view illustrating the configuration of a nonvolatile memory device manufactured by the method for manufacturing a nonvolatile memory device according to the second embodiment of the invention.
16A is a cross-sectional view taken along the line AA ′ of FIG. 15B, FIG. 16B is a cross-sectional view taken along the line BB ′ of FIG. 15B, and FIG. It is CC 'sectional drawing of FIG.15 (b), FIG.16 (d) is DD' sectional drawing of FIG.15 (b).
FIG. 17 is a schematic cross-sectional view in order of the processes, illustrating the method for manufacturing the nonvolatile memory device according to the second embodiment of the invention.
FIG. 18 is a schematic cross-sectional view in order of the steps, following FIG.
As illustrated in FIGS. 15 and 16, in the nonvolatile memory device 20 manufactured by the manufacturing method according to the second embodiment, a plurality of memory cell arrays are stacked in the Z-axis direction. Since the first memory cell array 101 can be the same as that described in the first embodiment, the description thereof is omitted.

In the nonvolatile memory device 20, the second memory cell array 201 is stacked on the first memory cell array 101 in the Z-axis direction.
The second memory cell array 201 includes a second electrode 140, a third electrode 240, and a second storage unit 230 provided between the second electrode 140 and the third electrode 240. The second electrode 140 in the second memory cell array 201 is also used as the second electrode 140 in the first memory cell array 101. The second electrode 140 is, for example, a word line, and the third electrode 240 is, for example, a bit line.

  In addition, the second storage unit 230 includes a second storage layer 232. The second memory layer 232 is a layer whose resistance changes according to at least one of an applied electric field and an energized current.

  The second storage unit 230 can further include a second rectifier element 231. In this specific example, the second rectifying element 231 is provided between the second electrode 140 and the second memory layer 232, but the second rectifying element 231 includes the third electrode 240, the second memory layer 232, and the like. The stacking order is arbitrary.

  The second storage unit 230, the second storage layer 232, the second rectifier element 231, and the third electrode 240 include the first storage unit 130, the first storage layer 132, the first rectifier element 131, and the first electrode 110 (or the first electrode 110). Since the configurations and materials described with respect to the two electrodes 140) can be applied, description thereof will be omitted.

  16A to 16D, the second memory cell 235 formed between the second electrode 140 and the third electrode 240 is surrounded by a second made of silicon oxide or the like. An interlayer insulating film 280 is embedded.

  A method for manufacturing the nonvolatile memory device 20 having such a configuration will be described with reference to FIGS.

  First, as illustrated in FIG. 17, the first electrode film 110 f to be the first electrode 110 and the first memory film 130 f to be the first memory section 130 are stacked on the main surface 106 of the substrate 105. (Step S210 illustrated in FIG. 14). Then, the first electrode film 110f and the first memory portion film 130f are processed into a strip shape extending in the first direction (step S220). At this time, the first memory portion film 130f may be processed into a tapered shape.

  Then, a sacrificial layer 181 is embedded between the processed first electrode film 110f and the first memory portion film 130f (step S230). For example, a novolac resin is used as the sacrificial layer 181.

  Then, the second electrode film 140f to be the second electrode 140 and the second memory film 230f to be the second memory part 230 are stacked on the first memory part film 130f and the sacrificial layer 181 (Step S240). ). The second memory portion film 230f includes, for example, a second rectifying element film 231f that becomes the second rectifying element 231 and a second memory layer film 232f that becomes the second memory layer 232.

  Then, a mask layer 150 having an etching rate slower than that of the sacrificial layer 181 is formed on the second memory portion film 230f (step S250). As the mask layer 150, for example, silicon oxide is used.

  Then, using the mask layer 150 as a mask, the second electrode film 140f and the second memory portion film 230f are processed into a strip shape extending in the second direction (step S260). Then, using the mask layer 150 as a mask, the portion of the first memory portion film 130f exposed from the sacrificial layer 181 is processed into a columnar shape having side walls along the first direction and side walls along the second direction (step S270). ).

  At this time, as illustrated in FIG. 17C, in the cross section taken along the line CC ′ of FIG. 15B, the first memory portion film 130 f has a tapered shape, and the first memory in that portion is formed. Since the partial film 130f is covered with the sacrificial layer 181, the portion where the first memory film 130f is covered with the sacrificial layer 181 remains without being etched.

Then, as shown in FIG. 18, the sacrificial layer 181 is removed, and the first memory portion film 130f covered with the sacrificial layer 181 is exposed (step S271).
When a novolac resin is used as the sacrificial layer 181, the sacrificial layer 181 can be removed using plasma using oxygen gas or a mixed gas of oxygen and ammonia, for example.

  At this time, since the sacrificial layer 181 is provided with, for example, a novolac resin having a higher etching rate than the mask layer 150 (eg, silicon oxide), the sacrificial layer 181 is formed without substantially damaging the mask layer 150. Can be removed.

Then, the exposed first memory portion film 130f is removed (step S272).
Then, for example, the mask layer 150 is removed, and the sacrificial layer 181 is removed by isotropic etching with plasma containing, for example, oxygen, ammonia, hydrogen, water, etc., and then the first electrode film 110f, between the first memory portion film 130f and the second electrode film 140f, silicon oxide to be the first interlayer insulating film 180 is buried by a technique such as CVD or SOG.
Thereby, the first-layer memory cell array 101 can be formed.

  At this time, the first interlayer insulating film 180 is provided, for example, to a depth from the substrate 105 to the second electrode 140, and a second sacrificial layer made of, for example, a novolac resin is formed on the first interlayer insulating film 180, and then A third electrode film to be the third electrode 240 is formed on the second memory portion film 230f and the second sacrificial layer, and the third electrode film is processed in the same manner as the first memory cell array 101. Then, the non-volatile memory device 20 illustrated in FIGS. 15 and 16 can be manufactured by processing the second memory portion film 230f into a columnar shape and then embedding the second interlayer insulating film 280.

  As described above, the manufacturing method according to the present embodiment can manufacture the nonvolatile memory device 20 in which two layers of memory cell arrays are stacked and the second electrode 140 is shared between the first layer and the second layer. However, it is possible to reduce processing defects in the memory portion between the wirings and improve the yield.

  In the above description, the case where two layers of memory cell arrays are stacked has been described. However, the method for manufacturing a nonvolatile memory device according to this embodiment can be applied to a nonvolatile memory device in which an arbitrary number of memory cell arrays are stacked.

FIG. 19 is a schematic perspective view illustrating the configuration of another nonvolatile memory device manufactured by the nonvolatile memory device manufacturing method according to the second embodiment of the invention.
As shown in FIG. 19, another nonvolatile memory device 21 manufactured by the manufacturing method according to the present embodiment has four memory cell arrays stacked. That is, the nonvolatile memory device 21 includes first to fourth memory cell arrays 101, 201, 301, and 401. The configuration of each memory cell array is the same as that of the nonvolatile memory devices 10 and 20.

  That is, the third memory cell array 301 includes the third electrode 240, the fourth electrode 340, and the third storage unit 330 provided between the third electrode 240 and the fourth electrode 340. The third storage unit 330 includes a third storage layer 332 and a third rectifying element layer 331.

  The fourth memory cell array 401 includes a fourth electrode 340, a fifth electrode 440, and a fourth storage unit 430 provided between the fourth electrode 340 and the fifth electrode 440. The fourth storage unit 430 includes a fourth storage layer 432 and a fourth rectifying element layer 431.

  The third electrode 240 is shared by the second memory cell array 201 and the third memory cell array 301, and the fourth electrode 340 is shared by the third memory cell array 301 and the fourth memory cell array 401.

  As described above, the nonvolatile memory device having the memory cell array of three or more layers and sharing the electrodes between the stacked memory cell arrays also applies the manufacturing method of the nonvolatile memory device according to the second embodiment. Can be manufactured.

  In the case of a nonvolatile memory device in which memory cell arrays are stacked and electrodes are not shared between the stacked memory cell arrays, it can be manufactured by applying the method for manufacturing the nonvolatile memory device according to the first embodiment. .

  The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, a specific configuration of each element such as a substrate, an electrode, a storage unit, a storage layer, a rectifying element, and an interlayer insulating film constituting a nonvolatile memory device can be appropriately selected from a known range by those skilled in the art. Are included in the scope of the present invention as long as they can be carried out in the same manner and the same effects can be obtained.

  Moreover, what combined any two or more elements of each specific example in the technically possible range is also included in the scope of the present invention as long as the gist of the present invention is included.

  In addition, based on the method for manufacturing a nonvolatile memory device described above as an embodiment of the present invention, all methods for manufacturing a nonvolatile memory device that can be implemented by a person skilled in the art with appropriate design changes are also included in the gist of the present invention. As long as it is included, it belongs to the scope of the present invention.

  In addition, in the category of the idea of the present invention, those skilled in the art can conceive of various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

10, 20, 21 Nonvolatile memory device 101 First memory cell array 105 Substrate 106 Main surface 110 First electrode 110f First electrode film 130 First memory portion 130f First memory portion film 131 First rectifier element 131f First rectifier element film 132 first memory layer 132f first memory layer film 135 first memory cell 140 second electrode 140f second electrode film 150 mask layer 180 first interlayer insulating film 181 sacrificial layer 182 first cap layer 190 interlayer insulating film 201 second memory Cell array 230 Second memory portion 230f Second memory portion film 231 Second rectifier element 231f Second rectifier element film 232 Second memory layer 232f Second memory layer film 235 Second memory cell 240 Third electrode 280 Second interlayer insulating film 301 Third memory cell array 330 Third storage unit 331 Third rectifying element 332 Third storage Layer 340 Fourth electrode 401 Fourth memory cell array 430 Fourth memory unit 431 Fourth rectifier 432 Fourth memory layer 440 Fifth electrode

Claims (7)

A plurality of first electrodes extending in a first direction; a plurality of second electrodes extending in a second direction non-parallel to the first direction and provided on the first electrode; A non-volatile memory having a first memory portion, which is provided between the first electrode and the second electrode and has a first memory layer whose resistance is changed by at least one of an applied electric field and an energized current A device manufacturing method comprising:
Laminating a first electrode film to be a first electrode and a first memory part film to be a first memory part on a main surface of the substrate;
Processing the first electrode film and the first memory film into a strip extending in a first direction;
Burying a sacrificial layer between the processed first electrode film and the first memory film;
Forming a second electrode film to be a second electrode on the first memory film and the sacrificial layer;
Forming a mask layer having an etching rate slower than that of the sacrificial layer on the second electrode film;
Using the mask layer as a mask, processing the second electrode film into a strip shape extending in a second direction;
Using the mask layer as a mask, a portion of the first memory portion film exposed from the sacrificial layer is removed, and the first memory portion film is made to have a side wall along the first direction and a side wall along the second direction. A step of processing into a column having
Removing the sacrificial layer to expose the first memory film covered by the sacrificial layer;
Removing the exposed first memory film;
A method for manufacturing a nonvolatile memory device, comprising: A plurality of first electrodes extending in a first direction; a plurality of second electrodes extending in a second direction non-parallel to the first direction and provided on the first electrode; Extending in a third direction non-parallel to the second direction, provided between the plurality of third electrodes provided on the second electrode, the first electrode and the second electrode, An electric field provided between the first memory portion having the first memory layer whose resistance changes according to at least one of an applied electric field and an energized current, and the second electrode and the third electrode. And a second memory unit having a second memory layer whose resistance changes according to at least one of the energized currents, and a method for manufacturing a nonvolatile memory device,
Laminating a first electrode film to be a first electrode and a first memory part film to be a first memory part on a main surface of the substrate;
Processing the first electrode film and the first memory film into a strip extending in a first direction;
Burying a sacrificial layer between the processed first electrode film and the first memory film;
Laminating a second electrode film to be a second electrode and a second memory film to be a second memory part on the first memory part film and the sacrificial layer;
Forming a mask layer having a slower etching rate than the sacrificial layer on the second memory film;
Using the mask layer as a mask, processing the second electrode film and the second memory film into a strip extending in a second direction;
Using the mask layer as a mask, a portion of the first memory portion film exposed from the sacrificial layer is removed, and the first memory portion film is made to have a side wall along the first direction and a side wall along the second direction. A step of processing into a column having
Removing the sacrificial layer to expose the first memory film covered by the sacrificial layer;
Removing the exposed first memory film;
A method for manufacturing a nonvolatile memory device, comprising:   By processing the first electrode film and the first memory film into a strip shape extending in the first direction, the first memory film on the side of the first electrode film with respect to the first direction 3. The non-volatile device according to claim 1, wherein a length in a vertical direction is longer than a length in a direction perpendicular to the first direction on a side opposite to the first electrode film. Of manufacturing a volatile memory device.   The sacrificial layer is an organic material, and the mask layer is any one selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide. A method for manufacturing the nonvolatile memory device according to claim 1.   The method of manufacturing a nonvolatile memory device according to claim 1, wherein the sacrificial layer is silicon oxide, and the mask layer is one of silicon nitride and silicon carbide. .   After the sacrificial layer is embedded between the processed first electrode film and the first memory film, the sacrificial layer is formed between the processed first electrode film and the first memory film. 6. The method for manufacturing a nonvolatile memory device according to claim 1, wherein a cap layer having an etching rate slower than that of the layer is embedded. The removal of the sacrificial layer is a treatment using a plasma containing a gas having at least one of the group consisting of O ₂ , H ₂ , H ₂ O, NH ₃ and CH ₄ . 6. A method for manufacturing a nonvolatile memory device according to any one of items 6 to 6.

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