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JP3660854B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
JP3660854B2
JP3660854B2 JP2000111466A JP2000111466A JP3660854B2 JP 3660854 B2 JP3660854 B2 JP 3660854B2 JP 2000111466 A JP2000111466 A JP 2000111466A JP 2000111466 A JP2000111466 A JP 2000111466A JP 3660854 B2 JP3660854 B2 JP 3660854B2
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Prior art keywords
semiconductor device
resin
lead
semiconductor
cutting
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JP2001298144A (en
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誠 中嶋
直樹 藤田
昭夫 三上
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Renesas Technology Corp
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Renesas Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/48147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置及びその製造方法に関し、特に、底面端子型の半導体装置に適用して有効な技術に関するものである。
【０００２】
【従来の技術】
半導体集積回路装置では、微細化の進展によって、より多くの回路を単一の半導体チップに搭載する高集積化が進められている。しかしながら、半導体集積回路を構成する全ての素子を単一チップに集積した場合には、モデルチェンジ等に伴う些細な仕様変更の度に、集積回路の再設計を行なうこととなり、迅速な対応が困難となる。そこで、こうした軽微な変更に対応するために、トランジスタ等回路素子の一部を集積化せずに実装基板上で半導体集積回路に外付けする構成とし、この外付けする回路素子を変えることによって、同一の半導体集積回路装置を用いたままで軽微な変更に対応する方法が採用されている。
【０００３】
そして、半導体分野においては、顧客実装面積・容積縮小を目的とした個別半導体装置の薄型化・小型化が常に求められている。こうした単体の回路素子にも小型化が求められており、例えば単体のトランジスタでは、顧客要求により外形寸法１００６（平面形状１ｍｍ×０．６ｍｍ）、或いは外形寸法０８０４（平面形状０．８ｍｍ×０．４ｍｍ）といった微小な半導体装置が求められている。
【０００４】
こうした半導体装置を製造する方法としては、例えば、特開平１１‐１０２９２４号公報に、セラミック又はガラスエポキシ樹脂の基板を用い、トランスファーモールド方式またはポッティング方式によって樹脂封止を行ない、封止後にダイシングにより切断・分離して個別の半導体装置を形成する技術が記載されている。
【０００５】
この技術では、半導体装置は、多層のセラミック基板の上面に形成された搭載部に、半導体素子のダイボンディングを行い、半導体素子の電極パッドとセラミック基板の電極端子とをボンディングワイヤにより接続し、前記電極端子が基板の底面に形成された外部端子と基板の内部配線によって接続され、半導体素子、基板の上面及び内側面、ボンディングワイヤを樹脂を用いた封止体によって封止してある。
【０００６】
この半導体装置の製造方法では、複数の半導体装置の基板が行列状に複数連続して形成されており、個々の半導体装置のダイボンディング・ワイヤボンディングが行なわれた後に、基板上面の複数の半導体素子及びボンディングワイヤ等を樹脂により一括して封止した後、ダイシングを用いて夫々切断し個別半導体装置を形成する。
【０００７】
この技術では、モールド時のゲート寸法に係らず、個別半導体の外形寸法の縮小が可能となる。しかし、セラミック基板のコストが従来のＣｕ、４２アロイ等を材料としたリードフレームに比べて高価であり、加えて基板表面には、金等の高価なメッキを導体として施さなければならないので製造原価が上昇する。また、セラミックは焼結材料の為、セラミック基板の焼成工程にて、焼成後の収縮誤差及び反りの問題が生じ、基板の歩留まり向上に限界がある等のデメリットが有り、更に、この結果、基板不具合部に不良処置（マーキング等）を施し、ダイボンディング時には不良部分にダイボンドを行なわないように工夫する等の処理が増加することとなる。
【０００８】
また、セラミック基板を用いた場合、セラミックが脆性をもっているために、上下金型により挟持しクランプ圧力を付加した時点で、若干の基板の反りによっても破損するおそれがあるので、従来方式である金型を用いたスルーモールド方式の採用は困難であり、レジンを塗布する等の別方法を用いる必要がある。レジンを塗布する場合、塗布の厚み及び平坦度の制御が難しくなる等の問題点が残っている。更に、基板上面を一括して樹脂封止する為、樹脂の収縮作用により分割前に大きな反りを生ずる。更には、ダイシング方法等に依って切削切断したパッケージの側面（セラミックと樹脂との接合界面）より水分が進入し、完成品の長期信頼性に影響を及ぼす可能性が有る等の問題点が、発明者等により明らかとなった。
【０００９】
他に、例えば特開平１０‐３１３０８２公報には、リードフレームに複数の半導体素子を搭載し、トランスファーモールド方式又はポッティング方式を用いて一括樹脂封止し、ダイシングによって個別の半導体装置に切断・分離する方法が開示されている。
【００１０】
しかしながらこの方法では、基板上面を一括して樹脂封止する為、比較的広い面積を１つのキャビティとして封止することとなり、封止後に樹脂が硬化する際の収縮作用による応力によって、樹脂の分割前に大きな大きな反りやねじれが生じてしまう。加えて、半導体素子の搭載されるアイランド下面及びリード電極下面が、半導体装置下面に露出する為、個別半導体装置の封止体としては封止体下面部の絶縁範囲を広くすることが難しい。その結果として、実装基板の回路設計時にアイランド下面及びリード電極下面と配線との電気的ショートを回避する配慮が必要となる。半導体装置の下に位置する基板領域に配線を通すことが難しくなり、回路設計の自由度が低下する。また、搭載する半導体素子がパッケージ寸法に近くなるに連れて、アイランド寸法を大きくする必要があり、アイランド部とリード電極との距離を十分に確保することが次第に困難となる。
【００１１】
更に、前記半導体装置外形の一部は、封止体の絶縁材料が硬化した後に切断された面によって構成されるため、切断面からの水分の進入による個別半導体装置の封止信頼性低下という問題が残っている。また、個別半導体装置に切断する際の作業性及び切断精度に関して充分な検討が為されていない等の問題点も有る。
【００１２】
【発明が解決しようとする課題】
こうした問題点を踏まえて、本発明者等は、個々の半導体装置に用いられるアイランド或いはリードの組を複数組一体に形成したリードフレームに、複数の半導体素子のダイボンディングを行ない、複数の半導体素子を列毎に一つのキャビティとして一体に封止体をモールドし、前記キャビティ及びリードフレームを切断して、個別の半導体装置に分離する技術を発明し、特願平１１‐１９９８９７号として出願した。
【００１３】
この技術では、個別の半導体装置に分離する際に、キャビティの樹脂とリードフレームの金属をダイシングブレードを用いて同時に切断しているが、切断時の応力によって金属と樹脂との接合面に亀裂の生じることがある。この亀裂が大きい場合には半導体素子の接合界面又はワイヤボンディング接合部に達し不良品となり、亀裂が小さい場合にも温度サイクル・吸湿等の影響によって経時的に半導体装置の信頼性を低下させることがある。
【００１４】
また、ダイシングブレードによって金属を切断する場合には、特に銅等の比較的軟らかい金属の場合には、切断面にダレと通称される上下方向への変形が生じ、この変形が底面に設けられる外部電極の端部に生じた場合には、電極面の平坦度が低下し、実装不良を生じることがある。
【００１５】
また、用いるブレードは樹脂と金属とを併せて切断するのでブレードを何れかに最適化することができないため、銅等の比較的軟らかい金属をリードフレームに用いた場合等には、この切断の際にブレードに金属の目づまりが生じることがあり、場合によっては、こうした目づまりによって分離工程の進捗が影響を受けることがある。
【００１６】
本発明の課題は、こうした問題を解決し、微小な半導体装置の封止体を比較的容易に低コストで行ない得る技術の更なる信頼性及び生産性の向上を図ることにある。
【００１７】
本発明の前記ならびにその他の課題と新規な特徴は、本明細書の記述及び添付図面から明らかになるであろう。
【００１８】
【課題を解決するための手段】
本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば下記の通りである。
【００２０】
アイランドに固定した半導体素子とリードとを接続し封止体によって封止した半導体装置の製造方法では、個々の半導体装置に用いられるアイランド或いはリードの組を行列状に複数組設け、行方向に隣接するアイランド或いはリードを連続させて一体に形成したリードフレームを用意し、このリードフレームの各アイランドに夫々半導体素子のダイボンディングを行ない、前記夫々の半導体素子と前記リードとを電気的に接続し、半導体素子、アイランド及びリードを封止する前記封止体を、列毎に複数を一体に一つのキャビティとして樹脂モールドし、前記封止体の列間の樹脂及びリードフレームをプレス切断し、前記封止体の行間のキャビティをブレード切断して個別の半導体装置に分離する。
【００２１】
かかる本発明によれば、半導体素子寸法に近似した半導体装置（ＣＳＰ：チップサイズパッケージ）に関し、個別半導体素子搭載基板として金属材料を用いたリードフレームの使用が可能となり、セラミック基板を用いた場合より安価に製造することができる。
【００２２】
また、半導体装置下面に、絶縁層を樹脂モールド方法により形成したことにより、実装基板上に形成された回路配線との電気的短絡を防止することができる。
【００２３】
また、リードフレームをプレス切断するので、前記ダイシングによるダレの発生を防止することができるので、実装不良の発生を防止することができる。
【００２４】
更に、ブレードを用いた切断では樹脂のみを切断するので、用いるブレードを樹脂の切断に最適化することが可能となり、切断を円滑に進捗させることができる。
【００２５】
加えて、複数の半導体素子を列毎に一つのキャビティとして樹脂封止することによって、熱または樹脂の収縮作用による反りを防止しつつ、仕上がり寸法精度の良い個別半導体装置を提供することが可能となる。
【００２６】
【発明の実施の形態】
以下、本発明の実施の形態を説明する。なお、実施の形態を説明するための全図において、同一機能を有するものは同一符号を付け、その繰り返しの説明は省略する。
【００２７】
（実施の形態１）
図１は本発明の一実施の形態である半導体装置を封止体を透過して示す斜視図であり、図２は本発明の一実施の形態である半導体装置を示す斜視図及びその底面の投影図である。
【００２８】
本実施の形態の半導体装置では、単結晶シリコン等の半導体基板にＦＥＴ等の所定の素子を形成した半導体素子１を、例えば金等のロー材によってアイランド２に固定し、半導体素子１とリード３とをボンディングワイヤ４によって接続してある。半導体素子１をダイボンディングするアイランド２には下面部内方及び外方に凹部が設けられ、リード３には下面部外方に凹部が設けられている。
【００２９】
半導体素子１、アイランド２、リード３の上面及び側面、ボンディングワイヤ４は、例えばエポキシ樹脂にフィラを混入させた封止樹脂を用いた封止体５によって封止され、前記下面部の凹部も封止体５によって覆われており、アイランド２及びリード３の外端部の下面或いは角部には凹部が設けられている。アイランド２の上面と半導体素子１の裏面電極とは導電性の接続がされており、アイランド２の下面及びリード３の下面が封止体５の底面から選択的に露出して半導体装置の外部電極となる。
【００３０】
封止体５の短手方向に沿った側面（以下、短側面という）下部にはわずかに張出した平坦部５ａが形成されており、この平坦部５ａではアイランド２及びリード３の端部上面及び外端部が露出しているが、アイランド２或いはリード３の端部は、封止体５の長手方向に沿った側面（以下、長側面という）には露出していない。
【００３１】
封止体５から露出して外部電極となるアイランド２の部分及びリード３の部分の厚さは、封止体５から露出しないアイランド２の部分及びリード３の部分の厚さよりも厚い構造となっており、アイランド２の下面内方に凹部を形成し、樹脂封止を行うことによって半導体装置の下面部電極間の絶縁層を広げることが可能となり、実装基板の回路配線との電気的短絡防止ができる。この結果、半導体装置実装基板設計時、パッケージ下面絶縁部に回路配線を配置することが可能となり、実装基板の縮小化に寄与することができる。
【００３２】
また、アイランド２とリード３との下面部外方に凹部を設け、外端の下面を夫々内側に後退させることによって、半導体装置の底面では、アイランド２及びリード３の電極として機能する露出面が封止体５と同一平面となり、かつその周囲が封止体５によって囲まれている。このため外部電極はアイランド２及びリード３の露出面に施されたメッキの厚さ分周囲の封止体５から均等に浮き出た形状となり、ハンダ付け等による実装基板への実装を確実に行なうことができる。
【００３３】
続いて、本実施の形態の半導体装置の製造方法について、図３乃至図１４を用いて説明する。
【００３４】
図３は本実施の形態の半導体装置の製造に用いられるリードフレームを示す平面図であり、図４は図３中のａ部を拡大して示す平面図及び縦断面図である。リードフレーム６には、図４中に破線にて示す封止体５形成領域毎に、個別の半導体装置となる夫々のアイランド２及びリード３が、行列状に連続的に形成してある。夫々のアイランド２及びリード３は、行方向にアイランド２とリード３とが交互に配置され、列方向には隣接する封止領域間にて即ち封止領域外で連結されている。
【００３５】
リードフレーム６としては、銅系または鉄系の材料を用いるので、多層セラミック基板を用いる場合に比べて、半導体素子寸法に近似した半導体装置の材料費を抑制することができる。
【００３６】
先ず、リードフレーム６のアイランド２上に半導体素子１が適切な接合ロー材によってダイボンディングされる。この際、リードフレーム下面のアイランド２の凹部に対応させて凹凸を設けたヒートブロックによって接触加熱されることによってリードフレーム６は適切な接合温度条件下に保持される。ダイボンディング後、ボンディングワイヤ４により半導体素子１の電極パッドとリード３の上面とを電気的に接続するワイヤボンディングを行なう。このダイボンディング及びワイヤボンディング作業はリードフレーム６に配置した全てのアイランド２及びリード３に対して施される。
【００３７】
こうしてダイボンディング及びワイヤボンディングを完了したリードフレーム６をトランスファーモールド装置の下金型にセットし、その後、上金型によりリードフレーム６を挟み込み、封止樹脂を注入し、各列を夫々一つのキャビティ７として、その列に並ぶ複数の半導体素子１を一体に封止する樹脂封止を行なう。
【００３８】
この樹脂封止では、リードフレーム６下面の凹部にも樹脂が十分に充填される様に行い、この凹部に充填された封止樹脂は、個別半導体装置に分割した後は、半導体装置底面の絶縁層の役割を果たす。各キャビティ７に充填した半導体封止用樹脂を硬化させた後、次工程前に不要な樹脂部分であるランナ７ａ及びゲート７ｂを切除する。この状態の平面図を図５に示し、図５中のａ部を拡大した平面図及び縦断面図を図６に、斜視図を図７に示す。なお、図５中ではキャビティ７、ランナ７ａ及びゲート７ｂ以外の樹脂が充填される部分に斜線を付してある。
【００３９】
本実施の形態では一列に並んだ複数の封止体５を列毎に一つのキャビティ７として樹脂封止することによって、封止樹脂の硬化時に生ずる収縮に影響されて、リードフレーム６が行方向に湾曲或いは反って、全体が変形するのを防止することができる。この結果、リードフレーム６の大型化が可能となり、取得数を増やすことができる。なお、キャビティ７列間にキャビティ７と平行にリードフレームの略全幅にわたってスリットを設けることによって、熱応力或いは封止後の樹脂硬化の過程において生じるレジン収縮等の変形を抑制することも可能である。
【００４０】
また、例えば一つの列に形成される半導体装置の数が多いためにキャビティ７が長くなると列方向にレジンの反りが生じる場合がある。そうした場合には、キャビティ７を列方向に分割する。即ち、複数の半導体装置を列毎に樹脂封止するキャビティ７を列方向に複数形成する構成とすることも可能である。
【００４１】
次に、アイランド２及びリード３のキャビティ７から露出する部分が半導体装置の外部電極となるリードフレーム６下面にハンダ等のメッキを施す。このメッキに先立って液体ホーニング等の処理によるメッキ付着面に付着した樹脂等の異物の除去を行う。この浄化処理によって封止体５とリードフレーム６との間に隙間が生じることがある。また、リードフレーム６を、予めパラジウムメッキ等の方法を用いて比較的軟質な材料で予め覆っておくことも可能であり、このような処理を施すことによって、この軟質材料が謂わばパッキングとして機能し、モールド時に樹脂が外部電極面へ付着するのを防止することができる。このパラジウムメッキ等の方法を用いれば、前記異物除去処理を省略することが可能であり、封止体５とリードフレーム６との間に前記異物除去処理によって隙間が生じるのを防止することができる。
【００４２】
更に、基板実装の際のハンダ付け性を向上させるため、外部電極面にハンダメッキ等のメッキ処理を行なう。前記のように予めリードフレームにパラジウム等がメッキされている場合には、パラジウムメッキがハンダ付け性に優れているため、外部電極面のハンダ等のメッキ処理を省略して、工程数を削減することも可能である。なお最近では、パラジウムメッキのハンダ付け性を更に高めるため、パラジウムメッキ表面に金をフラッシュ処理する場合もある。
【００４３】
次工程にて、封止樹脂表面等に製品名等を刻印（マーキング）した後に、列毎に一つのキャビティ７として封止されている複数の半導体装置を個別の半導体装置に分割する。その手順を以下に説明する。
【００４４】
先ず、図８の（ａ）に示すように、各キャビティ７の平坦部を上金型８及び下金型９で挟み、切断金型１０によってプレス切断する。この際、また、切断部分のリードフレーム６は下面に凹部が設けられて切断面積が小さくされているため、容易にキャビティ７樹脂とリードフレーム６の金属とをプレス切断することができる。プレス切断によってキャビティ７列間の不用部分を除去した状態を図８の（ｂ）及び図９に示す。
【００４５】
また、こうした切断によって、切断面に切断方向に沿って小さな突起（バリと通称されている）が生じることがある。このような突起が実装面である底面に向かって形成された場合には、半導体装置と実装基板との間に間隙が生じ、実装不良となることがある。本実施の形態では、半導体装置のアイランド２及びリード３の下面部外方に、夫々凹部を設けてあるのでアイランド２或いはリード３の端部は、三方を封止体５によって挟まれ上面を上金型８によって抑えられているために、切断の際に前記突起が生じにくくなり、突起が生じた場合にも半導体装置の底面から突出することがない。更に、本実施の形態では底面側から切断金型１０がプレス切断するため、このようなバリが生じたとしても、突起が底面側に生じないため実装不良の原因とはならない。また、アイランド２及びリード３が、前記凹部によって封止体５に強固に保持されることとなり、外部より加えられた力によってアイランド２或いはリード３が剥離・脱落或いは接合部分への亀裂の発生等が生じにくくなる。
【００４６】
なお、切断部分の樹脂がリードフレーム６と比べて薄い場合、或いは切断部分の金属部分の断面積が大きい場合等には、リードフレーム６とキャビティ７との間に剥離の生じる可能性が高くなる。こうした場合には、このプレス切断に先立って、図１０に平面図を図１１に部分拡大平面図及び断面図を示すように、切断部分に溝１１を形成しておいてもよい。溝１１としては、アイランド２或いはリード３の薄い部分を切断し、その凹部に充填された封止体５の樹脂が露出する程度が望ましい。この溝１１を設けることによって、図１２の（ａ）に示すように金型８，９，１０を用いたプレス切断によってキャビティ７に加えられるストレスを更に低減させることができる。また、封止に用いられる樹脂は金属と比較して脆性体であるため、溝を設けることによって、プレス切断が容易になる。こうした溝は、図１２の（ｂ）に示すように、ブレード１２を用いたダイシングによって容易に形成することができる。
【００４７】
次に、粘着性のダイシングテープにリードフレーム６下面（外部電極面）を貼り付け、更にその周囲をリング状のテープホルダーに固定する。ダイシングテープとしては、後の剥離工程で粘着成分がリードフレーム６下面に残り難いもの、例えば紫外線照射型のテープ（所謂ＵＶテープ）が望ましい。続いて、ダイシング位置合わせスリットを基準としてダイシング装置（ウエーハダイシング装置の流用が可能：図示せず）によって、図１３及び図１４に示すように、個別半導体装置に切削分割する。切削方法としては、半導体ウエーハ切断時に常用されている所謂フルカットダイシング方法を用い、ブレード１２を用いてキャビティ７は完全に切断するが、ダイシングテープ１２は部分的に切断し一体化したままとする。リードフレーム６に切断目標となる位置合わせ認識マークとしてスリット或いは貫通孔（図面中には記載せず）を施しておくことによって、樹脂封止、フレームハンダメッキを施した後、ダイシングにて個別半導体装置に切断する過程において、切断寸法精度を保証することができる。
【００４８】
このダイシングでは、キャビティ７の樹脂のみを切断する。樹脂は金属と比較して脆性体であるため、樹脂のみの切断はダイシングを迅速に行なうことが可能であり、また、切断する樹脂に最適化したブレード１２を用いることが可能となるため、ブレード１２の目づまりも生じにくい。更に、ダイシングテープに貼り付けた状態でフルカット方法により切断するため、切断後の個別半導体装置が飛散することなく、その位置関係もずれることはない為、その後の扱いが容易になる。
【００４９】
また、従来のスルーモールド方式により、半導体素子別にキャビティを形成する場合、封止体サイズが小さくなる程、封止樹脂導入路であるゲートを小さく構成しなければならず、レジン注入の観点からその限界寸法がある。本方式によれば、後に不要部分を切削切断すれば良いので、ゲートのサイズによって制約されることがない。また、多層セラミック基板を用いた場合との比較では、セラミックが脆性材料である点或いは基板焼成過程において若干の変形が生じている点を考慮すると、従来の金型を用いたトランスファーモールド方法により樹脂封止することは困難であるが、本願発明の如くリードフレームを用いた場合にはこの様な懸念はない。
【００５０】
この後、各半導体装置の電気的特性を測定する。この測定では、分離された各半導体装置が接着された状態の前記テープホルダーを、複数枚一組にリングカセットに入れた状態で選別工程のハンドリング装置のローダー部にセットする。セットされたテープホルダーは、一枚毎にハンドリング装置のローディング部に移送する。ハンドリング装置は、従来のダイレクトピックアップ方式のダイボンダと同様の構成であり、リングホルダと協働する個別半導体装置突き上げ機構を具備し、予め設定された座標位置または認識装置の認識結果から指定された座標位置データに基づき、突き上げ動作を行いダイシングテープより所定の半導体装置を引き剥がす。なお引き剥がす際には、紫外線照射型のダイシングテープを用いた場合は、紫外線照射を適量行い半導体装置底面とダイシングテープとの接合強度を弱めることによって、粘着成分が半導体装置底面に残存するのを防止することができる。
【００５１】
（実施の形態２）
図１５は本発明の他の実施の形態である半導体装置を示す斜視図であり、（ａ）はその外形を、（ｂ）は封止体を透過して内部を示してある。
【００５２】
本実施の形態の半導体装置では、単結晶シリコン等の半導体基板にＦＥＴ等の所定の素子を形成した半導体素子１を、例えば金等のロー材によってアイランド２に固定し、半導体素子１とリード３とをボンディングワイヤ４によって接続してある。半導体素子１をダイボンディングするアイランド２には下面部内方及び外方に凹部が設けられ、リード３には下面部外方に凹部が設けられている。
【００５３】
半導体素子１、アイランド２、リード３の上面及び側面、ボンディングワイヤ４は、例えばエポキシ樹脂にフィラを混入させた封止樹脂を用いた封止体１３によって封止されているが、本実施の形態の封止体１３では、単一の封止体１３に半導体素子１、アイランド２及びリード３の組が２組封止されている点が、前述した実施の形態とは相異しているが、他の構成は前述した実施の形態と同様である。
【００５４】
例えば、封止体１３の短手方向に沿った側面（以下、短側面という）下部にはわずかに張出した平坦部１３ａが形成されており、この平坦部１３ａではアイランド２及びリード３の端部上面及び外端部が露出しているが、アイランド２或いはリード３の端部は、封止体１３の長手方向に沿った側面（以下、長側面という）には露出しない構成となっている。このため、長側面側に隣接して形成される複数の半導体装置を、図１６に示すようにブレード１２による切断位置を変更するだけで、金型変更等をすることなしに、一体化することが可能となる。
【００５５】
封止される半導体素子としては、同種の素子を搭載して耐圧或いは許容電流を向上させることが可能となり、更に異種の素子、例えば発振回路の発振用の素子と増幅用の素子とを搭載してもよい。そして搭載した素子は、ボンディングワイヤ４によって互いにアイランド２或いはリード３を接続して必要な接続を行ない、回路としての配線長を短縮することも可能である。また、単一の封止体１２によって封止する、半導体素子１、アイランド２及びリード３の組を３組以上とする構成も可能である。
【００５６】
以上、本発明者によってなされた発明を、前記実施の形態に基づき具体的に説明したが、本発明は、前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲において種々変更可能であることは勿論である。
【００５７】
例えば、以上の説明では、主として本発明者によってなされた発明をその背景となった利用分野であるトランジスタについてレジン封止によるＣＳＰ(Chip Size Package)技術を適用した場合について説明したが、それに限定されるものではなく、本発明は、ダイオード或いはＱＦＮ型半導体装置等の他の形式の半導体装置にも広く適用が可能である。
【００５８】
【発明の効果】
本願において開示される発明のうち代表的なものによって得られる効果を簡単に説明すれば、下記の通りである。
（１）本発明によれば、半導体素子寸法に近似した半導体装置(ＣＳＰ)に関し、個別半導体素子搭載基板として金属材料を用いたリードフレームの使用が可能となるという効果がある。
（２）本発明によれば、微小な半導体装置の封止体を一括モールドによって樹脂封止することができるという効果がある。
（３）本発明によれば、上記効果（１）（２）により、半導体装置を安価に製造することができるという効果がある。
（４）本発明によれば、ダイシングによって、切断面に切断方向に沿って突起が生じるのを防止することができるという効果がある。
（５）本発明によれば、上記効果（４）により、実装不良の発生を防止することができるという効果がある。
（６）本発明によれば、、樹脂のみをブレード切断するため目づまりが生じにくく、分離工程の効率を向上させることができるという効果がある。
（７）本発明によれば、金属と樹脂との接合界面に亀裂が入りにくいので、耐湿性が向上するという効果がある。
（８）本発明によれば、複数の半導体素子を単一の封止体に封止した半導体装置を、金型の変更なしに製造することができるという効果がある。
（９）本発明によれば、半導体装置下面に、絶縁層を樹脂モールド方法により形成したことにより、実装基板上に形成された回路配線との電気的短絡を防止することができるという効果がある。
（１０）本発明によれば、複数の半導体素子を列毎に一つのキャビティとして樹脂封止することによって、熱または樹脂の収縮作用による反りを防止しつつ、仕上がり寸法精度の良い個別半導体装置を提供することが可能となるという効果がある。
【図面の簡単な説明】
【図１】本発明の一実施の形態である半導体装置を封止体を透視して示す斜視図である。
【図２】本発明の一実施の形態である半導体装置を示す斜視図及びその底面の投影図である。
【図３】本実施の形態に用いられるリードフレームを示す平面図である。
【図４】図３中のａ部を拡大して示す平面図及び断面図である。
【図５】本発明の一実施の形態である半導体装置を製造工程毎に示す平面図である。
【図６】図５中のａ部を拡大して示す平面図及び断面図である。
【図７】本発明の一実施の形態である半導体装置を製造工程毎に示す斜視図である。
【図８】本発明の一実施の形態である半導体装置を製造工程毎に示す断面図及び斜視図である。
【図９】本発明の一実施の形態である半導体装置を製造工程毎に示す平面図である。
【図１０】本発明の一実施の形態である半導体装置を製造工程毎に示す平面図である。
【図１１】図１０中のａ部を拡大して示す平面図及び断面図である。
【図１２】本発明の一実施の形態である半導体装置を製造工程毎に示す断面図及び斜視図である。
【図１３】本発明の一実施の形態である半導体装置を製造工程毎に示す平面図である。
【図１４】本発明の一実施の形態である半導体装置を製造工程毎に示す斜視図である。
【図１５】本発明の他の実施の形態である半導体装置を示す平面図である。
【図１６】本発明の他の形態である半導体装置の製造方法を示す斜視図である。
【符号の説明】
１…半導体素子、２…アイランド、３…リード、４…ボンディングワイヤ、５，１３…封止体、６…リードフレーム、７…キャビティ、７ａ…ランナ、７ｂ…ゲート、８…上金型、９…下金型、１０…切断金型、１１…溝、１２…ブレード。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a technique effective when applied to a bottom terminal type semiconductor device.
[0002]
[Prior art]
In semiconductor integrated circuit devices, with the progress of miniaturization, higher integration in which more circuits are mounted on a single semiconductor chip is being promoted. However, if all the elements that make up a semiconductor integrated circuit are integrated on a single chip, the integrated circuit must be redesigned each time a minor specification change occurs due to a model change, etc., making it difficult to respond quickly. It becomes. Therefore, in order to cope with such minor changes, a configuration in which a part of circuit elements such as transistors are externally attached to a semiconductor integrated circuit on a mounting substrate without being integrated, and by changing this externally attached circuit element, A method is adopted that can cope with minor changes while using the same semiconductor integrated circuit device.
[0003]
In the semiconductor field, there is a constant demand for thinner and smaller individual semiconductor devices for the purpose of reducing the customer mounting area and volume. Such single circuit elements are also required to be miniaturized. For example, in the case of a single transistor, an external dimension 1006 (planar shape 1 mm × 0.6 mm) or an external dimension 0804 (planar shape 0.8 mm × 0. 4 mm) is required.
[0004]
As a method of manufacturing such a semiconductor device, for example, in Japanese Patent Application Laid-Open No. 11-102924, a ceramic or glass epoxy resin substrate is used, resin sealing is performed by a transfer molding method or a potting method, and cutting is performed by dicing after sealing. A technique for separating and forming individual semiconductor devices is described.
[0005]
In this technique, a semiconductor device performs die bonding of a semiconductor element on a mounting portion formed on an upper surface of a multilayer ceramic substrate, connects an electrode pad of the semiconductor element and an electrode terminal of the ceramic substrate by a bonding wire, The electrode terminals are connected to the external terminals formed on the bottom surface of the substrate by the internal wiring of the substrate, and the semiconductor element, the top and inner surfaces of the substrate, and the bonding wires are sealed with a sealing body using a resin.
[0006]
In this semiconductor device manufacturing method, a plurality of semiconductor device substrates are continuously formed in a matrix, and a plurality of semiconductor elements on the upper surface of the substrate are formed after die bonding and wire bonding of each semiconductor device is performed. Then, the bonding wires and the like are collectively sealed with resin and then cut using dicing to form individual semiconductor devices.
[0007]
With this technology, it is possible to reduce the external dimensions of individual semiconductors regardless of the gate dimensions during molding. However, the cost of the ceramic substrate is higher than that of a conventional lead frame made of Cu, 42 alloy or the like, and in addition, the substrate surface must be subjected to expensive plating such as gold as a conductor. Rises. In addition, since ceramic is a sintered material, there are disadvantages such as shrinkage error and warpage after firing in the firing process of the ceramic substrate, and there is a limit in improving the yield of the substrate. Processing such as applying a defect treatment (marking or the like) to the defective part and devising not to perform die bonding on the defective part at the time of die bonding increases.
[0008]
In addition, when a ceramic substrate is used, since the ceramic is brittle, it may be damaged by slight warping of the substrate when it is sandwiched between upper and lower molds and clamp pressure is applied. It is difficult to adopt a through mold method using a mold, and it is necessary to use another method such as applying a resin. When a resin is applied, problems remain such as difficulty in controlling the thickness and flatness of the application. Furthermore, since the upper surface of the substrate is collectively sealed with resin, a large warp occurs before the division due to the shrinking action of the resin. Furthermore, there is a problem that moisture may enter from the side surface of the package cut and cut by the dicing method etc. (bonding interface between ceramic and resin), which may affect the long-term reliability of the finished product. It became clear by the inventors.
[0009]
In addition, for example, in Japanese Patent Application Laid-Open No. 10-313082, a plurality of semiconductor elements are mounted on a lead frame, encapsulated with a resin using a transfer mold method or a potting method, and cut and separated into individual semiconductor devices by dicing. A method is disclosed.
[0010]
However, in this method, since the upper surface of the substrate is sealed together with a resin, a relatively wide area is sealed as one cavity, and the resin is divided by the stress caused by the shrinkage when the resin is cured after sealing. A big big warp and twist occur before. In addition, since the island lower surface and the lead electrode lower surface on which the semiconductor element is mounted are exposed on the lower surface of the semiconductor device, it is difficult for the sealing body of the individual semiconductor device to widen the insulating range of the lower surface portion of the sealing body. As a result, consideration must be given to avoid an electrical short circuit between the lower surface of the island and the lower surface of the lead electrode and the wiring when designing the circuit of the mounting substrate. It becomes difficult to pass wiring through the substrate region located under the semiconductor device, and the degree of freedom in circuit design is reduced. Further, as the semiconductor element to be mounted becomes closer to the package size, it is necessary to increase the island size, and it becomes increasingly difficult to secure a sufficient distance between the island portion and the lead electrode.
[0011]
Furthermore, since a part of the outer shape of the semiconductor device is constituted by a surface that is cut after the insulating material of the sealing body is cured, there is a problem that the sealing reliability of the individual semiconductor device is reduced due to the ingress of moisture from the cut surface. Remains. In addition, there is a problem that sufficient study has not been made on workability and cutting accuracy when cutting into individual semiconductor devices.
[0012]
[Problems to be solved by the invention]
In light of these problems, the present inventors perform die bonding of a plurality of semiconductor elements on a lead frame in which a plurality of islands or lead groups used in individual semiconductor devices are integrally formed, and a plurality of semiconductor elements As a single cavity for each row, a sealing body is molded integrally, the cavity and the lead frame are cut, and a technique for separating them into individual semiconductor devices has been invented, and has been filed as Japanese Patent Application No. 11-199897.
[0013]
In this technology, when separating into individual semiconductor devices, the resin in the cavity and the metal in the lead frame are simultaneously cut using a dicing blade. However, the stress at the time of cutting causes cracks in the joint surface between the metal and the resin. May occur. If this crack is large, it reaches the bonding interface or wire bonding joint of the semiconductor element and becomes a defective product, and even if the crack is small, the reliability of the semiconductor device may deteriorate over time due to the influence of temperature cycle, moisture absorption, etc. is there.
[0014]
Also, when cutting a metal with a dicing blade, especially in the case of a relatively soft metal such as copper, a vertical deformation called sagging occurs on the cut surface, and this deformation is provided on the bottom surface. If it occurs at the end of the electrode, the flatness of the electrode surface may be reduced, resulting in poor mounting.
[0015]
In addition, since the blade to be used cuts both the resin and the metal, the blade cannot be optimized to any one. Therefore, when a relatively soft metal such as copper is used for the lead frame, etc. The blades may become clogged with metal, and in some cases, the clogging may affect the progress of the separation process.
[0016]
An object of the present invention is to solve these problems and to further improve the reliability and productivity of a technique capable of performing a sealing body of a minute semiconductor device relatively easily at low cost.
[0017]
The above and other problems and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0018]
[Means for Solving the Problems]
Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
[0020]
Semiconductor device in which semiconductor element fixed to island and lead are connected and sealed with sealing body In this manufacturing method, a plurality of pairs of islands or leads used in individual semiconductor devices are provided in a matrix, and a lead frame is prepared by integrally forming islands or leads adjacent in the row direction. Each of the islands is die-bonded to a semiconductor element, the semiconductor element and the lead are electrically connected, and a plurality of the sealing bodies for sealing the semiconductor element, the island, and the lead are provided for each column. The resin is integrally molded as one cavity, the resin and the lead frame between the columns of the sealing bodies are press-cut, and the cavities between the rows of the sealing bodies are blade-cut to be separated into individual semiconductor devices.
[0021]
According to the present invention, regarding a semiconductor device (CSP: chip size package) approximate to a semiconductor element size, a lead frame using a metal material can be used as an individual semiconductor element mounting substrate, which is more than when a ceramic substrate is used. It can be manufactured at low cost.
[0022]
In addition, since the insulating layer is formed on the lower surface of the semiconductor device by a resin molding method, an electrical short circuit with the circuit wiring formed on the mounting substrate can be prevented.
[0023]
In addition, since the lead frame is press-cut, the occurrence of sagging due to the dicing can be prevented, and the occurrence of mounting defects can be prevented.
[0024]
Furthermore, since the cutting using the blade cuts only the resin, the blade to be used can be optimized for cutting the resin, and the cutting can proceed smoothly.
[0025]
In addition, by sealing a plurality of semiconductor elements as a single cavity for each row, it is possible to provide an individual semiconductor device with good finished dimensional accuracy while preventing warping due to heat or resin shrinkage. Become.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.
[0027]
(Embodiment 1)
FIG. 1 is a perspective view showing a semiconductor device according to an embodiment of the present invention through a sealing body, and FIG. 2 is a perspective view showing the semiconductor device according to an embodiment of the present invention and the bottom surface thereof. FIG.
[0028]
In the semiconductor device of the present embodiment, a semiconductor element 1 in which a predetermined element such as an FET is formed on a semiconductor substrate such as single crystal silicon is fixed to an island 2 with a brazing material such as gold, and the semiconductor element 1 and the lead 3 Are connected by a bonding wire 4. The island 2 for die-bonding the semiconductor element 1 is provided with recesses inside and outside the lower surface portion, and the lead 3 is provided with a recess outside the lower surface portion.
[0029]
The semiconductor element 1, the island 2, the upper surface and side surfaces of the lead 3, and the bonding wire 4 are sealed by a sealing body 5 using a sealing resin in which filler is mixed with epoxy resin, for example, and the concave portion of the lower surface portion is also sealed. It is covered with the stationary body 5, and a recess is provided on the lower surface or corner of the outer end of the island 2 and the lead 3. The upper surface of the island 2 and the back surface electrode of the semiconductor element 1 are conductively connected, and the lower surface of the island 2 and the lower surface of the lead 3 are selectively exposed from the bottom surface of the sealing body 5 to external electrodes of the semiconductor device. It becomes.
[0030]
A slightly projecting flat portion 5a is formed at a lower portion of a side surface (hereinafter referred to as a short side surface) along the short direction of the sealing body 5. In the flat portion 5a, the upper surfaces of the end portions of the island 2 and the lead 3 and Although the outer end portion is exposed, the end portion of the island 2 or the lead 3 is not exposed on a side surface (hereinafter referred to as a long side surface) along the longitudinal direction of the sealing body 5.
[0031]
The thickness of the portion of the island 2 exposed from the sealing body 5 and serving as the external electrode and the portion of the lead 3 is thicker than the thickness of the portion of the island 2 and the portion of the lead 3 not exposed from the sealing body 5. By forming a recess on the inner surface of the island 2 and sealing the resin, it is possible to expand the insulating layer between the electrodes on the lower surface of the semiconductor device, thereby preventing electrical short circuit with circuit wiring on the mounting board. Can do. As a result, when designing a semiconductor device mounting board, circuit wiring can be arranged on the lower surface insulating portion of the package, which can contribute to the reduction of the mounting board.
[0032]
Further, by providing a recess outside the lower surface portion of the island 2 and the lead 3 and by retreating the lower surface of the outer end to the inside, an exposed surface that functions as an electrode of the island 2 and the lead 3 is formed on the bottom surface of the semiconductor device. It becomes the same plane as the sealing body 5 and its periphery is surrounded by the sealing body 5. For this reason, the external electrode has a shape that is evenly raised from the surrounding sealing body 5 by the thickness of the plating applied to the exposed surfaces of the island 2 and the lead 3, and the mounting to the mounting substrate by soldering or the like is surely performed. Can do.
[0033]
Next, a method for manufacturing the semiconductor device of this embodiment will be described with reference to FIGS.
[0034]
FIG. 3 is a plan view showing a lead frame used for manufacturing the semiconductor device of the present embodiment, and FIG. 4 is an enlarged plan view and a longitudinal sectional view showing a part a in FIG. In the lead frame 6, islands 2 and leads 3, which are individual semiconductor devices, are continuously formed in a matrix for each sealing body 5 formation region indicated by a broken line in FIG. 4. In each of the islands 2 and the leads 3, the islands 2 and the leads 3 are alternately arranged in the row direction, and are connected between adjacent sealing regions in the column direction, that is, outside the sealing region.
[0035]
Since the lead frame 6 is made of a copper-based or iron-based material, the material cost of the semiconductor device approximated to the semiconductor element dimensions can be suppressed as compared with the case where a multilayer ceramic substrate is used.
[0036]
First, the semiconductor element 1 is die-bonded on the island 2 of the lead frame 6 with an appropriate bonding material. At this time, the lead frame 6 is maintained under an appropriate bonding temperature condition by being contact-heated by a heat block provided with irregularities corresponding to the concave portions of the island 2 on the lower surface of the lead frame. After die bonding, wire bonding for electrically connecting the electrode pad of the semiconductor element 1 and the upper surface of the lead 3 by the bonding wire 4 is performed. The die bonding and wire bonding operations are performed on all islands 2 and leads 3 arranged on the lead frame 6.
[0037]
The lead frame 6 in which die bonding and wire bonding are thus completed is set in the lower mold of the transfer mold apparatus, and then the lead frame 6 is sandwiched by the upper mold, the sealing resin is injected, and each column is formed into one cavity. 7, resin sealing is performed to integrally seal a plurality of semiconductor elements 1 arranged in the row.
[0038]
This resin sealing is performed so that the recesses on the lower surface of the lead frame 6 are sufficiently filled with the resin. After the sealing resin filled in the recesses is divided into the individual semiconductor devices, the insulation of the bottom surface of the semiconductor device is obtained. Play the role of layer. After the semiconductor sealing resin filled in each cavity 7 is cured, the runner 7a and the gate 7b, which are unnecessary resin portions, are cut off before the next process. FIG. 5 shows a plan view of this state, FIG. 6 shows an enlarged plan view and a longitudinal sectional view of part a in FIG. 5, and FIG. 7 shows a perspective view. In FIG. 5, the portions other than the cavity 7, the runner 7 a, and the gate 7 b are filled with a hatched portion.
[0039]
In the present embodiment, a plurality of sealing bodies 5 arranged in a row are resin-sealed as one cavity 7 for each row, so that the lead frame 6 is affected in the row direction by being affected by shrinkage that occurs when the sealing resin is cured. Therefore, it is possible to prevent the entire structure from being bent or warped. As a result, the lead frame 6 can be enlarged and the number of acquisitions can be increased. In addition, it is possible to suppress deformations such as thermal stress or resin shrinkage that occurs in the process of resin curing after sealing by providing slits across the entire width of the lead frame in parallel with the cavities 7 between the seven rows of cavities. .
[0040]
Further, for example, since the number of semiconductor devices formed in one row is large, when the cavity 7 becomes long, the warping of the resin may occur in the row direction. In such a case, the cavities 7 are divided in the column direction. In other words, a plurality of cavities 7 for resin-sealing a plurality of semiconductor devices for each column may be formed in the column direction.
[0041]
Next, solder or the like is plated on the lower surface of the lead frame 6 where the portions exposed from the cavities 7 of the island 2 and the leads 3 serve as external electrodes of the semiconductor device. Prior to this plating, foreign substances such as resin adhering to the plating adhesion surface are removed by a process such as liquid honing. This purification process may cause a gap between the sealing body 5 and the lead frame 6. It is also possible to previously cover the lead frame 6 with a relatively soft material using a method such as palladium plating. By performing such treatment, the soft material functions as a so-called packing. In addition, it is possible to prevent the resin from adhering to the external electrode surface during molding. If this method such as palladium plating is used, the foreign matter removal process can be omitted, and a gap can be prevented from being generated by the foreign matter removal process between the sealing body 5 and the lead frame 6. .
[0042]
Furthermore, in order to improve the solderability at the time of board mounting, a plating process such as solder plating is performed on the external electrode surface. As described above, when palladium or the like is plated on the lead frame in advance, palladium plating is excellent in solderability. Therefore, the plating process such as soldering on the external electrode surface is omitted to reduce the number of processes. It is also possible. Recently, in order to further improve the solderability of palladium plating, gold may be flashed on the surface of the palladium plating.
[0043]
In the next step, a product name or the like is marked on the sealing resin surface or the like, and then a plurality of semiconductor devices sealed as one cavity 7 for each column are divided into individual semiconductor devices. The procedure will be described below.
[0044]
First, as shown in FIG. 8A, the flat portion of each cavity 7 is sandwiched between the upper mold 8 and the lower mold 9 and press-cut with a cutting mold 10. At this time, since the lead frame 6 of the cut portion is provided with a recess on the lower surface to reduce the cutting area, the cavity 7 resin and the metal of the lead frame 6 can be easily press-cut. FIG. 8B and FIG. 9 show a state where unnecessary portions between the seven rows of cavities are removed by press cutting.
[0045]
In addition, such cutting may cause small protrusions (commonly called burrs) along the cutting direction on the cut surface. When such a protrusion is formed toward the bottom surface, which is the mounting surface, a gap may be generated between the semiconductor device and the mounting substrate, resulting in mounting failure. In the present embodiment, the recesses are provided outside the lower surface of the island 2 and the lead 3 of the semiconductor device, so that the end of the island 2 or the lead 3 is sandwiched between three sides by the sealing body 5 and the upper surface is raised. Since it is restrained by the mold 8, the protrusion is less likely to occur during cutting, and even when the protrusion is generated, it does not protrude from the bottom surface of the semiconductor device. Further, in the present embodiment, the cutting die 10 is press-cut from the bottom surface side, and even if such a burr is generated, no protrusion is generated on the bottom surface side, so that it does not cause a mounting failure. In addition, the island 2 and the lead 3 are firmly held by the sealing body 5 by the concave portion, and the island 2 or the lead 3 is peeled off or dropped off due to a force applied from the outside, or a crack is generated in the joint portion. Is less likely to occur.
[0046]
When the resin at the cut portion is thinner than the lead frame 6 or when the cross-sectional area of the metal portion at the cut portion is large, there is a high possibility that peeling will occur between the lead frame 6 and the cavity 7. . In such a case, prior to the press cutting, the groove 11 may be formed in the cut portion as shown in FIG. 10 and a partially enlarged plan view and a sectional view in FIG. As the groove 11, it is desirable that the thin portion of the island 2 or the lead 3 is cut and the resin of the sealing body 5 filled in the concave portion is exposed. By providing the groove 11, the stress applied to the cavity 7 by press cutting using the molds 8, 9, and 10 can be further reduced as shown in FIG. In addition, since the resin used for sealing is a brittle body compared to metal, press cutting is facilitated by providing the groove. Such grooves can be easily formed by dicing using a blade 12 as shown in FIG.
[0047]
Next, the lower surface (external electrode surface) of the lead frame 6 is attached to the adhesive dicing tape, and the periphery thereof is fixed to a ring-shaped tape holder. As the dicing tape, a tape in which the adhesive component hardly remains on the lower surface of the lead frame 6 in a subsequent peeling step, for example, an ultraviolet irradiation type tape (so-called UV tape) is desirable. Subsequently, using a dicing alignment slit as a reference, the wafer is divided into individual semiconductor devices as shown in FIGS. 13 and 14 by a dicing device (possible use of a wafer dicing device: not shown). As a cutting method, a so-called full-cut dicing method commonly used in cutting a semiconductor wafer is used, and the cavity 7 is completely cut by using the blade 12, but the dicing tape 12 is partially cut and remains integrated. . A slit or through-hole (not shown in the drawing) is provided on the lead frame 6 as an alignment recognition mark to be a cutting target, and after resin sealing and frame solder plating, individual semiconductors are diced. In the process of cutting into the apparatus, the cutting dimensional accuracy can be guaranteed.
[0048]
In this dicing, only the resin in the cavity 7 is cut. Since the resin is a brittle body compared to the metal, the cutting of only the resin can be performed quickly by dicing, and the blade 12 optimized for the resin to be cut can be used. 12 clogs are less likely to occur. Furthermore, since it cut | disconnects by the full cut method in the state affixed on the dicing tape, the individual semiconductor device after a cutting | disconnection does not scatter, and the positional relationship also does not shift | deviate, Therefore The subsequent handling becomes easy.
[0049]
Further, when the cavity is formed for each semiconductor element by the conventional through mold method, the smaller the sealing body size, the smaller the gate that is the sealing resin introduction path must be configured. There are critical dimensions. According to this method, unnecessary portions may be cut and cut later, so that there is no restriction by the size of the gate. Also, in comparison with the case of using a multilayer ceramic substrate, considering that the ceramic is a brittle material or that some deformation has occurred in the substrate firing process, the resin is formed by a transfer mold method using a conventional mold. Although it is difficult to seal, there is no such concern when a lead frame is used as in the present invention.
[0050]
Thereafter, the electrical characteristics of each semiconductor device are measured. In this measurement, the tape holder in a state where each separated semiconductor device is bonded is set in a loader portion of a handling device in a sorting process in a state where a plurality of tape holders are put in a ring cassette. The set tape holder is transferred to the loading unit of the handling device one by one. The handling device has the same configuration as a conventional direct pickup type die bonder, and includes an individual semiconductor device push-up mechanism that cooperates with the ring holder, and coordinates designated based on a preset coordinate position or a recognition result of the recognition device. Based on the position data, a push-up operation is performed to peel off a predetermined semiconductor device from the dicing tape. When peeling off, if an ultraviolet irradiation type dicing tape is used, an appropriate amount of ultraviolet irradiation is applied to weaken the bonding strength between the bottom surface of the semiconductor device and the dicing tape, so that the adhesive component remains on the bottom surface of the semiconductor device. Can be prevented.
[0051]
(Embodiment 2)
15A and 15B are perspective views showing a semiconductor device according to another embodiment of the present invention, in which FIG. 15A shows the outer shape and FIG. 15B shows the inside through the sealing body.
[0052]
In the semiconductor device of the present embodiment, a semiconductor element 1 in which a predetermined element such as an FET is formed on a semiconductor substrate such as single crystal silicon is fixed to an island 2 with a brazing material such as gold, and the semiconductor element 1 and the lead 3 Are connected by a bonding wire 4. The island 2 for die-bonding the semiconductor element 1 is provided with recesses inside and outside the lower surface portion, and the lead 3 is provided with a recess outside the lower surface portion.
[0053]
The semiconductor element 1, the island 2, the top and side surfaces of the lead 3, and the bonding wire 4 are sealed by a sealing body 13 using a sealing resin in which a filler is mixed in an epoxy resin, for example. This sealing body 13 is different from the above-described embodiment in that two sets of the semiconductor element 1, the island 2 and the lead 3 are sealed in a single sealing body 13. Other configurations are the same as those of the above-described embodiment.
[0054]
For example, a flat portion 13 a that slightly protrudes is formed at a lower portion of a side surface (hereinafter referred to as a short side surface) along the short direction of the sealing body 13, and the end portions of the island 2 and the lead 3 are formed in the flat portion 13 a. Although the upper surface and the outer end portion are exposed, the end portion of the island 2 or the lead 3 is configured not to be exposed on a side surface (hereinafter referred to as a long side surface) along the longitudinal direction of the sealing body 13. For this reason, a plurality of semiconductor devices formed adjacent to the long side surface can be integrated without changing the mold or the like only by changing the cutting position by the blade 12 as shown in FIG. Is possible.
[0055]
As a semiconductor element to be sealed, it is possible to improve the withstand voltage or allowable current by mounting the same type of element, and further mounting different types of elements, for example, an oscillation element and an amplification element of an oscillation circuit. May be. The mounted elements can be connected to each other by connecting the islands 2 or the leads 3 with the bonding wires 4 to shorten the wiring length as a circuit. In addition, a configuration in which three or more sets of the semiconductor element 1, the island 2, and the lead 3 sealed by the single sealing body 12 are possible is also possible.
[0056]
Although the invention made by the present inventor has been specifically described based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention. Of course.
[0057]
For example, in the above description, the case where the CSP (Chip Size Package) technology by resin sealing is applied to a transistor which is a field of use that is based on the invention made by the present inventor has been described. However, the present invention can be widely applied to other types of semiconductor devices such as diodes or QFN type semiconductor devices.
[0058]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
(1) According to the present invention, with respect to a semiconductor device (CSP) approximated to a semiconductor element size, there is an effect that a lead frame using a metal material can be used as an individual semiconductor element mounting substrate.
(2) According to the present invention, there is an effect that a sealing body of a minute semiconductor device can be resin-sealed by collective molding.
(3) According to the present invention, the effects (1) and (2) have an effect that a semiconductor device can be manufactured at low cost.
(4) According to the present invention, there is an effect that it is possible to prevent a protrusion from being formed along the cutting direction on the cut surface by dicing.
(5) According to the present invention, due to the effect (4), it is possible to prevent the occurrence of mounting defects.
(6) According to the present invention, since only the resin is blade-cut, clogging hardly occurs, and the efficiency of the separation process can be improved.
(7) According to the present invention, cracks are unlikely to occur at the joint interface between the metal and the resin, so that there is an effect of improving moisture resistance.
(8) According to the present invention, there is an effect that a semiconductor device in which a plurality of semiconductor elements are sealed in a single sealing body can be manufactured without changing the mold.
(9) According to the present invention, since the insulating layer is formed on the lower surface of the semiconductor device by the resin molding method, an electrical short circuit with the circuit wiring formed on the mounting substrate can be prevented. .
(10) According to the present invention, by sealing a plurality of semiconductor elements as a single cavity for each column, an individual semiconductor device with good finished dimensional accuracy can be obtained while preventing warping due to heat or resin shrinkage. There is an effect that it can be provided.
[Brief description of the drawings]
FIG. 1 is a perspective view illustrating a semiconductor device according to an embodiment of the present invention as seen through a sealing body.
FIG. 2 is a perspective view showing a semiconductor device according to an embodiment of the present invention and a projected view of the bottom surface thereof.
FIG. 3 is a plan view showing a lead frame used in the present embodiment.
4 is an enlarged plan view and a cross-sectional view of a part in FIG.
FIG. 5 is a plan view showing a semiconductor device according to an embodiment of the present invention for each manufacturing process;
6 is an enlarged plan view and a cross-sectional view showing a part a in FIG. 5;
FIG. 7 is a perspective view showing a semiconductor device according to an embodiment of the present invention for each manufacturing process;
FIGS. 8A and 8B are a cross-sectional view and a perspective view illustrating a semiconductor device according to an embodiment of the present invention for each manufacturing process; FIGS.
FIG. 9 is a plan view showing a semiconductor device according to an embodiment of the present invention for each manufacturing process;
FIG. 10 is a plan view showing a semiconductor device according to an embodiment of the present invention for each manufacturing process;
FIGS. 11A and 11B are a plan view and a cross-sectional view showing an enlarged portion a in FIG.
12A and 12B are a cross-sectional view and a perspective view illustrating a semiconductor device according to an embodiment of the present invention for each manufacturing process.
FIG. 13 is a plan view showing a semiconductor device according to an embodiment of the present invention for each manufacturing process;
FIG. 14 is a perspective view showing a semiconductor device according to an embodiment of the present invention for each manufacturing process;
FIG. 15 is a plan view showing a semiconductor device according to another embodiment of the present invention.
FIG. 16 is a perspective view showing a method for manufacturing a semiconductor device according to another embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Semiconductor element, 2 ... Island, 3 ... Lead, 4 ... Bonding wire, 5, 13 ... Sealing body, 6 ... Lead frame, 7 ... Cavity, 7a ... Runner, 7b ... Gate, 8 ... Upper metal mold, 9 ... lower mold, 10 ... cutting mold, 11 ... groove, 12 ... blade.

Claims (3)

アイランドに固定した半導体素子とリードとを接続し封止体によって封止した半導体装置の製造方法において、
個々の半導体装置に用いられるアイランド或いはリードの組を行列状に複数組設け、行方向に隣接するアイランド或いはリードを連続させて一体に形成したリードフレームを用意し、このリードフレームの各アイランドに夫々半導体素子のダイボンディングを行なう工程と、
前記夫々の半導体素子と前記リードとを電気的に接続する工程と、
半導体素子、アイランド及びリードを封止する前記封止体を、列毎に複数を一体に一つのキャビティとして樹脂モールドする工程と、
前記封止体の列間の樹脂及びリードフレームをプレス切断する工程と、
前記封止体の行間のキャビティをブレード切断して個別の半導体装置に分離する工程とを有することを特徴とする半導体装置の製造方法。In a method for manufacturing a semiconductor device in which a semiconductor element fixed to an island and a lead are connected and sealed by a sealing body,
A plurality of pairs of islands or leads used in individual semiconductor devices are provided in a matrix, and lead frames are prepared by integrally forming islands or leads adjacent in the row direction. A step of die bonding a semiconductor element;
Electrically connecting each of the semiconductor elements and the leads;
A step of resin-molding the sealing body that seals the semiconductor element, the island, and the lead as a single cavity in a single unit for each row;
Pressing the resin and the lead frame between the rows of the sealing bodies; and
And a step of blade-cutting the cavities between the rows of the sealing bodies to separate them into individual semiconductor devices. 前記ブレード切断する工程は、前記キャビティを構成する樹脂封止体のみを切断し、前記切断によって形成される封止体の一対の側面には、前記リードが露出しないことを特徴とする請求項１に記載の半導体装置の製造方法。2. The blade cutting step includes cutting only a resin sealing body constituting the cavity, and the leads are not exposed on a pair of side surfaces of the sealing body formed by the cutting. The manufacturing method of the semiconductor device as described in any one of Claims 1-3 . 前記切断によって形成される封止体の一対の側面と直交する一対の側面には、前記リードの端部が露出することを特徴とする請求項２に記載の半導体装置の製造方法。 A pair of the side surface, a method of manufacturing a semiconductor device according to 請 Motomeko 2 you and an end portion of the lead is exposed perpendicular to the pair of side surfaces of the sealing member to be formed by the cutting.
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