JP3535186B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to miniaturization of a semiconductor device.

[0002]

2. Description of the Related Art Today, an FA is used as a flash memory which does not require a contact in a cell array and can be downsized.
A CE (FLASH ARRAY CONTACTLESS EPROM) cell structure flash memory is known.

FIG. 6 shows the structure of the FACE cell 50. F
In the ACE cell 50, an n ⁺ type drain 3 and an n ⁺ type source 4 are provided in a p type silicon well 2 provided in a substrate. A channel region 16 is between the drain 3 and the source 4. A tunnel oxide film 8 is provided on the channel region 16. Furthermore, the floating gate 12 made of polysilicon and the interlayer insulating film 1 are formed on the tunnel oxide film 8.
3 and the control gate electrode 14 are sequentially provided.

Writing and erasing of information in the FACE cell 50 will be described. When writing information "1", a high voltage is applied to the control gate electrode 14 and the drain 3, and a ground potential is applied to the source 4 and the well 2. As a result, the hot electrons generated near the drain 3 jump over the potential barrier of the tunnel oxide film 8 and flow into the floating gate 12. As a result, the information “1” is written in the FACE cell 50.

On the other hand, when the information "0" is stored (erased) in the FACE cell 50, the floating gate 12
In order to return the electrons that have flown into the source 4 to the source 4, a high voltage is applied between the floating gate 12 and the source 4 in the direction opposite to that at the time of writing information. As a result, an electric field in the opposite direction to that at the time of writing is generated, and FN (Fowler-Nordhei
m) The electrons are pulled back to the source 4 by tunneling.

[0006] By thus returning the electrons,
The threshold value of the control gate voltage for forming a channel in the channel region 16 drops. This state
This is a state in which the information "0" is stored in the FACE cell 50 (hereinafter referred to as non-writing state).

Next, the reading operation of information in the non-volatile memory FACE cell 50 will be described. First, the sense voltage Vs is applied to the control gate electrode 14. The sense voltage Vs is an intermediate voltage between the threshold voltage in the written state and the threshold voltage in the non-written state.

When the FACE cell 50 is in the write state, the sense voltage Vs is higher than the threshold voltage of the FACE cell 50.
, The channel is not formed in the channel region 16. Therefore, even if the potential of the source 4 is higher than that of the drain 3, no current flows between the drain 3 and the source 4.

On the other hand, when the FACE cell 50 is in the non-written state, the sense voltage Vs is higher than the threshold voltage of the FACE cell 50, so that a channel is formed in the channel region 16. Therefore, by setting the potential of the drain 3 higher than the potential of the source 4, a current flows between the drain 3 and the source 4.

As described above, in the FACE cell 50, at the time of reading, by applying the sense voltage Vs to the control gate electrode 14, it is detected whether or not a channel is formed in the channel region 16, and it is determined whether or not the channel is in the written state. It is possible to determine whether it is in the non-written state.

Next, referring to FIG. 7, the FACE cell 50
The manufacturing method of will be described. A thermal oxide film 80 (pad oxide) is formed on the surface of the p-type silicon well 2 of the semiconductor substrate, a silicon nitride film is formed thereon by a chemical vapor deposition (CVD) method, and then a photoresist is used. And selectively etch to form a silicon nitride film 82 having an opening 81. This state is shown in FIG. 7A. From this state, arsenic (As) is ion-implanted into the entire surface of the semiconductor substrate as shown in FIG. 7B. As a result, arsenic ions are implanted into the semiconductor substrate region 101 of the opening 81 not covered with the silicon nitride film 82.

Next, by heat-treating the semiconductor substrate, oxidation progresses only in a portion not covered with the silicon nitride film 82, and a selective oxide film 5 having a bird's beak structure is formed at the end as shown in FIG. 7C. It At the same time, this heat treatment forms an n ⁺ -type source 4 which is a buried diffusion layer in the p-type silicon well 2 below the selective oxide film 5.

Next, after removing the silicon nitride film 82 and the thermal oxide film 80, as shown in FIG. 7D, a tunnel oxide film 8 is formed on the surface of the substrate by diluting and oxidizing the thin film.
After that, the floating gate 12, the interlayer insulating film 13, and the control gate electrode 14 are formed (see FIG. 6).

As described above, in the FACE cell 50, since the source 4 is formed as the buried diffusion layer in the semiconductor substrate, no contact is required, and the source 4 and the selective oxide film 5 are formed in a self-aligned manner. Therefore, the cell area can be reduced.

[0015]

However, the FACE cell 50 as described above has the following problems.

In the FACE cell 50, a bird's beak structure portion is formed at the end of the selective oxide film 5. The bird's beak structure portion is formed so as to spread laterally up to the portion covered with the silicon nitride film 82. For this reason,
As shown in FIG. 8, the source 4 and the floating gate 1
The film thickness of the portion functioning as the tunnel oxide film in the overlapping portion with 2 becomes thicker, the electric field is weakened accordingly, and the FN tunneling current is reduced.

Of course, the n ⁺ region of the source 4 is diffused by the heat treatment for forming the selective oxide film 5, and the source 4
The width α1 of the source 4 may be wider than the width β1 of the selective oxide film 5 in the lateral direction, and the end portion of the source 4 may overtake the bird's beak structure portion. However, in this case, there arises a problem that the impurity concentration of the source 4 becomes low. When such a decrease in the impurity concentration occurs, a depletion layer is generated when a high voltage is applied to the source 4 during erasing, and the tunnel oxide film 8 becomes substantially thicker, which is equivalent to the electric field. Weakened F-N
There is a problem that the current decreases.

When the selective oxide film 5 is formed, if the silicon nitride film 82 is thick, the thermal oxide film 80 (pad oxide) is thin, and the oxidation temperature is high, the bird's beak is laterally moved. You can make sure it doesn't spread. However, such a process places a great deal of stress on the semiconductor substrate.

That is, the above FACE cell manufacturing method could not solve both the problems of reducing the cell area and reducing the impurity concentration of the source region. It is an object of the present invention to solve the above problems and to provide a semiconductor device capable of preventing lateral expansion of a buried diffusion layer and improving the degree of integration.

[0020]

[Means for Solving the Problems] 1)Semiconductor according to the present invention
A method of manufacturing a body device includes a semiconductor substrate and the semiconductor substrate
Selection with bird's beak structure provided on the surface and both ends
An oxide film and a substrate area below the selective oxide film
A buried source region and a bar near both ends of the selective oxide film are formed.
Tons provided on the substrate surface near both ends of the ozbeak structure
The channel oxide film and the conductive film provided on the tunnel oxide film.
A method for manufacturing a semiconductor device including an electric layer, comprising: A )
Cover the surface of the semiconductor substrate with a mask having an opening,
An impurity implantation step of implanting impurities from the opening, B ) The above
Selective oxide film with bird's beak structure at both ends in the opening
And fill the area where impurities are implanted.
A buried source region forming step of forming a source region,
C ) Below both ends of the bird's beak structure of the selective oxide film
Until a part of the buried source region of the part is exposed.
Wet etch to remove the selective oxide film almost uniformly
The bird's beak structure parts at both ends are removed by
The buried source region exposing step to be removed, D ) Said exposed
An insulating thin film forming step of forming an insulating thin film on the substrate surface,
E ) A conductor forming a conductor layer via the insulating thin film
Layer forming process, F ) As soon as possible after the insulating thin film forming step,
The width of the buried source region is larger than the width of the selective oxide film.
It also has a process to perform heat treatment to spread
To do.

2) In the method of manufacturing a semiconductor device according to the present invention, the removal of the bird's beak structure portion of the selective oxide film in the buried source region exposing step is performed by an etchant having an etching action only on the selective oxide film. It is characterized by being performed.

3) Manufacturing method of semiconductor device according to the present invention
Covers the surface of the semiconductor substrate with a mask having an opening,
Impurity injection step of injecting impurities from the opening, forming a selective oxide film having a bird's beak structure at the end in the opening, and performing buried diffusion narrower than the lateral width of the selective oxide film in the impurity injected portion. A step of forming a buried diffusion layer for forming a layer, a step of removing at least the bird's beak structure of the selective oxide film to expose a part of the buried diffusion layer, and a step of forming an insulating thin film on the surface of the substrate. A method of manufacturing a semiconductor device, comprising: an insulating thin film forming step; and a conductor layer forming step of forming a conductor layer via the insulating thin film , wherein a flattening film is formed in the embedded diffusion layer exposing step. After that, with respect to the semiconductor substrate, the selective oxide film and the planarization film,
Using the etching rate is almost the same etchant, line removal of the bird's beak structure part of said selective oxide film by the buried diffusion layer is etched to expose the
At the earliest, after the insulating thin film forming step, the embedding
Heat is applied so that the width of the diffusion layer is wider than the width of the selective oxide film.
It is characterized by including a step of performing a treatment. 4) The method of manufacturing a semiconductor device according to the present invention is characterized in that the bird's beak structure portion of the selective oxide film is removed by etching the semiconductor substrate for a predetermined amount.

[0023]

5) Manufacture of a flash memory according to the present invention
In the manufacturing method, the conductor layer is a floating gate.
And further forming an interlayer insulating film on the conductor layer.
Forming step, forming a control electrode on the interlayer insulating film
And a control electrode forming step.

6) Method of manufacturing transistor according to the present invention
Method, the conductor layer is a gate electrode.
Characterize.

[0026]

[0027]

1) In the method of manufacturing a semiconductor device according to the present invention, A ) a mask having an opening is used to
And an impurity injection step of injecting impurities from the opening,
B ) Selective acid with bird's beak structure at both ends in the opening
Form the oxide film and fill in the part where impurities are injected
Embedded source region forming process for forming a buried source region
Degree, C) under both ends of the bird's beak structure portion of the selective oxidation layer
Select until part of the embedded source region is exposed
Wet etching is performed so that the oxide film is scraped almost uniformly.
By removing the bird's beak structure parts at both ends.
Embedded source region exposure process, D ) Exposed substrate surface
Insulating thin film forming process to form insulating thin film on E, insulation
Conductive layer forming step of forming a conductive layer via a conductive thin film,
F ) After the insulating thin film formation process at the earliest, the buried source region
Heat treatment is performed so that the width of the area is wider than the width of the selective oxide film.
It is equipped with a process. This allows the bird's edge to be thin.
The oxide film on both ends of the beak structure is removed,
A part of the buried source region at the bottom of the part is exposed. Also,
Since the insulating thin film is formed on the exposed substrate surface,
Embedding without expanding the embedded source region laterally
It is possible to form an insulating thin film on the edge of the source region.
Wear. Also, the bird's beak structure part is etched once.
After that, heat treatment is performed, so the embedded source region
Embedded source region without widening
The insulating thin film can be surely formed on the edge of the area.
It

2) In the method of manufacturing a semiconductor device according to the present invention, the bird's beak structure portion of the selective oxide film is removed by an etchant having an etching action only on the selective oxide film. Therefore,
The bird's beak structure portion of the selective oxide film can be easily removed.

3) In the method of manufacturing a semiconductor device according to the present invention, the surface of the semiconductor substrate is covered with a mask having an opening.
And an impurity injection step of injecting impurities from the opening,
Selective oxide film with bird's beak structure at the end is formed in the opening.
Selective oxidation is performed on the part where impurities are injected while forming
Buried to form a buried diffusion layer narrower than the lateral width of the film
Diffusion layer forming step, at least bird's beak of selective oxide film
The structure part is removed and a part of the buried diffusion layer is exposed.
Embedded diffusion layer exposure process, forming an insulating thin film on the substrate surface
Insulating thin film forming process, the conductor through the insulating thin film
Of a semiconductor device including a conductor layer forming step of forming a layer
It is a manufacturing method, and is flattened in the step of exposing the buried diffusion layer.
After forming the film, semiconductor substrate, selective oxide film and planarization
Etchant with almost the same etching rate as the film
Etch until the buried diffusion layer is exposed using
By removing the bird's beak structure part of the selective oxide film
And at the earliest after the insulating thin film formation process, buried diffusion
Heat treatment is performed so that the width of the layer is wider than the width of the selective oxide film.
It is equipped with a process. 4) Manufacturing of semiconductor device according to the present invention
In the method, the semiconductor substrate is etched for a predetermined amount.
By removing the bird's beak structure part of the selective oxide film,
To do. Therefore, it is possible to prevent a step from being formed on the substrate surface after the removal of the bird's beak structure portion. Also,
After first etching the structure portion, heat treatment is performed.
Therefore, the embedded diffusion layer is expanded so much in the lateral direction.
The insulating thin film on the edge of the buried diffusion layer without
It can really be formed.

[0030]

5) In the method for manufacturing a flash memory according to the present invention, the conductor layer is a floating gate.
In addition, an interlayer insulating film is formed on the conductor layer.
Process, control electrode type that forms control electrode on interlayer insulating film
Equipped with a forming process. Therefore, by applying a predetermined voltage to the control electrode, a tunneling current can be generated at a low voltage between the floating gate and the buried source region.

[0032]

[0033]

[0034]

EXAMPLE An example of the present invention will be described. Figure 2
The FACE cell 51 manufactured by the manufacturing method which is one example of the present invention is shown in FIG.

In the FACE cell 51, an n ⁺ type drain 3 and an n ⁺ type source 4 which are buried diffusion layers are provided in a p type silicon well 2 provided in the substrate. Both the drain 3 and the source 4 are low-concentration impurity regions n ^−.
Has an area. A well region between the drain 3 and the source 4 is a channel region 16, and a tunnel oxide film 8 which is an insulating thin film is provided on the channel region 16.
Further, a floating gate 12, which is a conductor layer, an interlayer insulating film 13, and a control gate electrode 14 are sequentially provided on the tunnel oxide film 8.

The control gate electrode 14 and the source 4, and the control gate electrode 14 and the drain 3 are insulated by the selective oxide film 5.

Next, a method of manufacturing the FACE cell 51 will be described with reference to FIG. A thermal oxide film 80 (pad oxide) is formed on the surface of the p-type silicon well 2 of the semiconductor substrate,
After that, a silicon nitride film is formed by the CVD method, and then selectively etched using a photoresist,
A silicon nitride film 82 that is a mask having an opening 81 is formed. This state is shown in FIG. 1A. From this state, arsenic (As) is ion-implanted into the entire surface of the semiconductor substrate. As a result, arsenic ions are implanted into the semiconductor substrate region 101 of the opening 81 not covered with the silicon nitride film 82.

Next, by heat-treating the semiconductor substrate, the oxidation proceeds only in the portion not covered with the silicon nitride film 82, and the selective oxide film 5 having the bird's beak structure 5a at the end as shown in FIG. 1B is 400 nm thick. Is formed by. At the same time, by this heat treatment, in the p-type silicon well 2 below the selective oxide film 5, a buried diffusion layer n ^{+ is formed.}
A mold source 4 is formed.

Next, as shown in FIG. 1C, the silicon nitride film 82 is removed. After that, etching is performed with an etchant having an etching action only on the silicon oxide film. In this example, hydrofluoric acid was used as the etchant. As a result, as shown in FIG. 1D, the selective oxide film 5 becomes 200 nm, the bird's beak structure portion 5a is removed, and a part of the source 4 is exposed.

In this embodiment, the bird's beak structure portion 5 of the selective oxide film 5 is formed by wet etching.
Although a is etched, it may be removed by dry etching.

In this state, the surface of the substrate was diluted with 1 by oxidation.
A tunnel oxide film 8 of 0 nm is formed. As a result, the surface of the substrate including a part of the source 4 is covered with the tunnel oxide film 8.

Next, a 150 nm polysilicon layer is formed by the CVD method, and etching is performed using a photoresist to form the floating gate 12 as shown in FIG. 1F.

Next, a silicon oxide film,
An interlayer insulating film 13 composed of a silicon nitride film and a silicon oxide film is formed. In this example, the lowermost silicon oxide film was formed by dilute oxidation, the silicon nitride film was formed by the low pressure CVD method, and the uppermost silicon oxide film was formed by wet oxidation.

Next, the interlayer insulating film 1 is formed by the CVD method.
A polysilicon layer having a thickness of 300 nm is formed on the photoresist layer 3 and is etched using a photoresist to form a control gate electrode 14 as shown in FIG. In this way, the FACE cell 51 is formed.

As described above, in the present embodiment, since the tunnel oxide film is formed after the bird's beak structure portion 5a is once etched, the source 4 is not expanded in the lateral direction, and the upper portion of the end of the source 4 is not expanded. It is possible to form a silicon oxide film that functions as a tunnel oxide film. Further, since the treatment for preventing the bird's beak from spreading in the lateral direction is unnecessary, there is no stress on the semiconductor substrate.

By the way, generally, in thermal oxidation, the oxidation rate at which an oxide film is formed increases as the impurity concentration of the semiconductor increases. Therefore, as for the film thickness of the tunnel oxide film 8, as shown in FIG. 3A, the film thickness t1 on the source 4 may be larger than the film thickness t2 on the substrate. Therefore, the heat treatment may be performed again after the tunnel oxide film 8 is formed in FIG. 1E.

By this re-heat treatment, as shown in FIG. 3B, the n ⁺ region of the source 4 is diffused so that the width α2 of the source 4 becomes wider than the width β2 of the selective oxide film in the lateral direction, and Bird's beak structure part 5a at the end (see FIG. 1C)
Can be overtaken.

In this case, since the heat treatment is performed after the bird's beak structure portion 5a is once etched, it is not necessary to extend the source 4 as the buried diffusion layer so much in the lateral direction. Therefore, the insulating thin film functioning as a tunnel oxide film can be reliably formed on the end portion of the source 4. Further, since the treatment for preventing the bird's beak from spreading in the lateral direction is unnecessary, there is no stress on the semiconductor substrate.

That is, the FACE cell manufacturing method according to the present embodiment can solve both the problems of reducing the cell area and reducing the impurity concentration of the source region.

In the present embodiment, etching is performed only on the silicon oxide film with an etchant having an etching action. Therefore, FIG.
As shown in FIG. Such a recess 8
8 causes a step when the floating gate 12 and the like are formed thereafter. When such a step occurs,
The electric field may be concentrated, and the reliability of the tunnel oxide film 8 may be reduced. Therefore, in order to avoid such a problem, it is preferable that the bird's beak structure portion 5a of the selective oxide film 5 extends smoothly. Therefore, when forming the selective oxide film 5, it is desirable that the silicon nitride film 82 be thin, the thermal oxide film 80 (pad oxide) be thick, and the oxidation temperature be low.

FIG. 4 shows another embodiment of the method for removing the bird's beak structure portion 5a. FIG. 4A shows the state of FIG. 1C. From this state, a flattening film 84 is formed as shown in FIG. 4B. Then, the bird's beak structure portion 5a of the selective oxide film 5 is removed from the semiconductor substrate 2, the selective oxide film 5, and the flattening film 84 by using an etchant having substantially the same etching rate. As a result, as shown in FIG. 4C, the bird's beak structure portion 5a is removed.

By removing the bird's beak structure portion 5a after forming the flattening film 84 in this manner, it is possible to prevent a step from being formed on the substrate surface after removing the bird's beak structure portion. Thereby, the concentration of the electric field can be prevented and the reliability of the tunnel oxide film 8 can be prevented from being lowered.

In this embodiment, a silicon oxide film is used as the flattening film 84. As a result, the etching rate of silicon and the silicon oxide film may be taken into consideration as an etchant.

Further, in this method, it is necessary to end the etching process when the semiconductor substrate is etched by a predetermined amount γ in the state of FIG. 4C, but the amount of silicon generated by the etching can be detected. Can be easily controlled.

In addition to the silicon oxide film, other materials,
For example, single crystal silicon, amorphous silicon, a silicon nitride film or the like may be used.

FIG. 5 shows a transistor 61 manufactured by using the present invention. In the transistor 61, an n ⁺ type drain 3 and an n ⁺ type source 4 are provided in a p-type silicon well 2. Both the drain 3 and the source 4 have an n ⁻ region which is a low concentration impurity region. A channel region 16 is provided between the drain 3 and the source 4, and a 40 nm gate oxide film 18, which is an insulating thin film, is provided on the channel region 16. Further, a gate electrode 15 which is a conductor layer is provided on the gate oxide film 18. Gate electrode 15
Is covered with an interlayer film 26. Source electrode 2 for source 4
4, the drain electrode 23 is connected to the drain 3.

The gate electrode 15 and the source 4, and the gate electrode 15 and the drain 3 are insulated by the selective oxide film 5.

As described above, the present invention is not limited to the flash memory and can be applied to any semiconductor device having a buried diffusion layer under the selective oxide film 5.

In the FACE cell manufacturing method, the bird's beak structure portion 5a is once etched and then heat-treated.
The heat treatment may be performed by omitting the etching step of a. This also eliminates the need for a treatment to prevent the bird's beak from spreading in the lateral direction, so that stress on the semiconductor substrate can be prevented.

[0060]

1) In the method of manufacturing a semiconductor device according to the present invention, both of the bird's beak structure portions of the selective oxide film are formed.
A portion of the buried source region below the edge is exposed.
To remove the selective oxide film almost evenly.
By birding, the bird's beak structure parts at both ends
Embedded source region exposure step to remove the exposed substrate
Insulating thin film forming process to form an insulating thin film on the surface, insulation
Conductive layer forming step of forming a conductive layer via a conductive thin film,
After the insulating thin film formation process at the earliest, the buried source region
Heat treatment to make the width wider than the width of the selective oxide film.
Be prepared. Therefore, the insulating thin film can be formed on the end portion of the embedded source region without laterally expanding the embedded source region. Also the bar
After the Zubik structure is once etched, heat treatment is performed.
Since the embedded source area
Above the edge of the buried source region without spreading
The limbic thin film can be reliably formed. This allows
It is possible to provide a semiconductor device capable of preventing lateral expansion of the embedded source region and improving the degree of integration.

2) In the method of manufacturing a semiconductor device according to the present invention, the bird's beak structure portion of the selective oxide film is removed by an etchant having an etching action only on the selective oxide film. Therefore,
A semiconductor device capable of improving the degree of integration can be easily provided.

3) In the method of manufacturing a semiconductor device according to the present invention , a flattening film is formed in the buried diffusion layer exposing step.
After the formation, the semiconductor substrate, selective oxide film and planarization film
On the other hand, use an etchant with almost the same etching rate.
And etch until the buried diffusion layer is exposed.
By removing the bird's beak structure part of the selective oxide film by
At the earliest, after the insulating thin film formation process, the buried diffusion layer
Heat treatment to make the width wider than the width of the selective oxide film.
Be prepared. 4) In the method of manufacturing a semiconductor device according to the present invention, the semiconductor substrate is etched by a predetermined amount to remove the bird's beak structure portion of the selective oxide film. Therefore, it is possible to prevent a step from being formed on the substrate surface after the removal of the bird's beak structure portion, and it is possible to provide a more reliable semiconductor device. Also,
After first etching the structure portion, heat treatment is performed.
Therefore, the embedded diffusion layer is expanded so much in the lateral direction.
The insulating thin film on the edge of the buried diffusion layer without
It can really be formed.

5) In the method for manufacturing a flash memory according to the present invention, the conductor layer is a floating gate.
In addition, an interlayer insulating film is formed on the conductor layer.
Process, control electrode type that forms control electrode on interlayer insulating film
Equipped with a forming process. Therefore, by applying a predetermined voltage to the control electrode, a tunneling current can be generated at a low voltage between the floating gate and the buried source region. Therefore, it is possible to provide a flash memory capable of preventing lateral expansion of the embedded source region and improving the degree of integration.

[0064]

[0065]

[Brief description of drawings]

FIG. 1 is a diagram showing a manufacturing process of a FACE cell 51.

FIG. 2 is a diagram showing a structure of a FACE cell 51.

FIG. 3 is a comparison diagram of a case where a heat treatment is performed and a case where a heat treatment is not performed after the tunnel oxide film 8 is formed.

FIG. 4 is a diagram showing another manufacturing method.

FIG. 5 is a diagram showing a structure of a transistor 61 manufactured by a manufacturing method according to the present invention.

FIG. 6 is a diagram showing a structure of a conventional FACE cell.

FIG. 7 is a diagram showing a manufacturing process of a conventional FACE cell.

FIG. 8 is a diagram showing details of a conventional FACE cell.

[Explanation of symbols]

3 ... Drain 4 ... Source 5 ... ・ ・ ・ Selective oxide film 5a ... Birds beak structure part 8 ... Tunnel oxide film 12 ... Floating gate 13 ... Interlayer insulating film 14 ... Control gate electrode 15 ... Gate electrode 81 ... Opening 82 ... Silicon nitride film

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-2-1988 (JP, A) JP-A-4-230078 (JP, A) JP-A-61-166079 (JP, A) JP-A-3- 270174 (JP, A) JP-A-4-211176 (JP, A) JP-A-4-42558 (JP, A) JP-A-63-260178 (JP, A) US Pat. No. 4780424 (US, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/8247 H01L 29/788 H01L 29/792

Claims (6)

(57) [Claims] 1. A semiconductor substrate, a selective oxide film provided on the surface of the semiconductor substrate and having bird's beak structures at both ends, a buried source region provided in a substrate region below the selective oxide film, and the selective oxidation. A method for manufacturing a semiconductor device , comprising: a tunnel oxide film provided on a substrate surface near both ends of a bird's beak structure near both ends of the film; and a conductor layer provided on the tunnel oxide film. ) Cover the surface of the semiconductor substrate with a mask having an opening,
Impurity implantation step of implanting impurities from the opening, B ) Forming a buried source region in which a selective oxide film having a bird's beak structure is formed at both ends in the opening and a buried source region is formed in a portion where the impurity is implanted Step C ) Wet-etching the selective oxide film so that the selective oxide film is substantially uniformly abraded until both of the buried source regions under both ends of the bird's beak structure portion of the selective oxide film are exposed. Step of exposing the buried source region for removing the structural portion, D ) Step of forming an insulating thin film on the exposed surface of the substrate, E ) Forming a conductive layer through the insulating thin film Step F ) After the insulating thin film forming step at the earliest, the embedding
The width of the source region should be wider than that of the selective oxide film.
A method of manufacturing a semiconductor device, comprising: 2. The method for manufacturing a semiconductor device according to claim 1, wherein the removal of the bird's beak structure portion of the selective oxide film in the buried source region exposing step is performed by an etchant having an etching action only on the selective oxide film. A method of manufacturing a semiconductor device, comprising: 3. An impurity implantation step of covering the surface of a semiconductor substrate with a mask having an opening, and implanting impurities from the opening; forming a selective oxide film having a bird's beak structure at an end in the opening; A step of forming a buried diffusion layer that is narrower than the lateral width of the selective oxide film in a portion where impurities are implanted, at least a bird's beak structure part of the selective oxide film is removed, and a part of the buried diffusion layer is exposed. A step of exposing the buried diffusion layer, a step of forming an insulating thin film on the surface of the substrate, a step of forming a conductive layer through the insulating thin film, and a step of forming a conductive layer; a method, wherein at buried diffusion layer exposing step, after forming the planarizing film, the semiconductor substrate, with respect to the selective oxide film and the planarization layer, edge Ngureto by using the approximately the same etchant, performs removal of the bird's beak structure part of said selective oxide film by the buried diffusion layer is etched to expose the insulating film forming step after at the earliest, the buried diffusion
Heat treatment so that the width of the layer is wider than the width of the selective oxide film.
A method of manufacturing a semiconductor device, comprising: 4. The method of manufacturing a semiconductor device according to claim 3, wherein the bird's beak structure portion of the selective oxide film is removed by etching the semiconductor substrate by a predetermined amount. 5. The method of any one of the claims 1 to claim 4, wherein the conductive layer is a floating gate, further forming an interlayer insulating film on the conductive layer And a control electrode forming step of forming a control electrode on the interlayer insulating film, the method of manufacturing a flash memory. 6. The method of any one of the claims 1 to claim 5, the manufacturing method of the transistor, wherein, said conductive layer is a gate electrode.