JP3518122B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention has an impurity concentration of 1 ×.
The present invention relates to a method for manufacturing a semiconductor device having an N ⁺ layer or a P ⁺ layer of 10 ¹⁹ / cm ³ and a semiconductor device having a silicon-based gate electrode structure containing impurities.

[0002]

2. Description of the Related Art In manufacturing various semiconductor circuits such as MOS type semiconductors and bipolar type semiconductors, it has been attempted to activate impurities in a diffusion layer or a polysilicon type gate electrode or to densify an insulating film. Heat treatment at a temperature of ℃ or more is performed in many steps. For example, in a MOS type semiconductor, in order to secure the reliability of a gate oxide film while performing a high temperature process, polysilicon (hereinafter referred to as Poly-Si) or polycide in which Poly-Si and metal silicide are stacked is used as a gate electrode thereof. However, even in the production of such a MOS type semiconductor, 700 ° C. is usually used for the purpose of activating impurities in Poly-Si.
The above heat treatment is performed. As such heat treatment at 700 ° C. or higher, there is a high temperature short time annealing (Rapid Thermal Anneal; hereinafter abbreviated as RTA) mainly for suppressing the diffusion of impurities and efficiently activating it. Is often implemented as a technique indispensable for manufacturing semiconductor devices.

[0003]

By the way, in manufacturing a semiconductor device, after the RTA is performed, high temperature long time annealing or high temperature CVD for the purpose of densification of an insulating film is performed.
In general, heat treatment at about 600 to 850 ° C. is performed during the process. However, when such a long-time heat treatment is performed after RTA, impurities once activated by RTA are inactivated again, and the resistance of Si that forms the diffusion layer or Poly-Si that forms the gate electrode is increased. Increase, or the gate electrode is depleted to deteriorate device characteristics, which leads to deterioration of the performance of the semiconductor device.

FIG. 11 shows the RTA at 1000 ° C. for 10 seconds.
After performing the above, the change in sheet resistance between the N ⁺ diffusion layer and the P ⁺ diffusion layer when post annealing is performed for 30 minutes is shown. Incidentally, N ⁺ diffusion layer, P ⁺ for ion implantation into the diffusion layer, N ⁺ in the diffusion layer of As ⁺ at 3 × 10 ¹⁵ / cm ^2, also P ⁺ In diffusion layer BF ₂ ⁺ a 4 × 10 ¹⁵ / cm ² respectively. From FIG. 11, in comparison with the case where post annealing is not performed, that is, only RTA is performed, especially 80
High temperature long time annealing at 0-850 ℃ (Post annealing)
It can be seen that the sheet resistance is significantly increased in the case of performing. Moreover, such a tendency similarly occurs also in a silicon-based gate electrode, for example, 800 ° C. after RTA.
When high temperature annealing for 30 minutes at 850 ° C. is performed, Poly-Si is depleted and the gate capacitance is reduced.

As a measure for preventing such inconvenience, the annealing temperature of the high temperature long time annealing is made higher than usual to lower the resistance value of the diffusion layer and the gate electrode and improve the depletion of the gate electrode. It is also possible to do. However, in that case, the depth (Xj) of the diffusion layer increases, and the short channel effect cannot be suppressed. Further, in the CMOS structure, when the N ⁺ gate of the NMOS and the P ⁺ gate of the PMOS are connected to each other, interdiffusion of impurities in the gate electrode occurs and the threshold voltage (Vth) varies (increases). This causes new inconvenience.

The present invention has been made in view of the above circumstances, and an object thereof is to suppress an increase in resistance of the N ⁺ layer or P ⁺ layer serving as a diffusion layer without causing fluctuation of the threshold voltage. And to provide a method of manufacturing a semiconductor device capable of improving depletion of a Poly-Si (polysilicon) -based gate electrode.

[0007]

[Means for Solving the Problems] Claim 1 in the present invention
In the method of manufacturing a semiconductor device described above , a gate is formed on the surface of the Si substrate.
Process of forming oxide film and reducing pressure on the gate oxide film
Amorphous silicon doped with phosphorus by the CVD method
The step of forming a silicon film and the amorphous silicon film
Forming a WSi _x film, WSi _x film and said Ammo
Pattern the rufus silicon film to form the gate electrode
And the step of implanting impurities into the Si substrate
Activate source and drain regions and activate impurities
And a heat treatment step to activate the impurities.
The heat treatment process for controlling the influence of the active state of the impurities
Of the heat treatment steps that affect
However, the heat treatment process for activating the impurities is 800.
The method for solving the above problems was to carry out the treatment at a temperature of ℃ to 1100 ℃ for 60 seconds or less .

Here, as the final heat treatment step ,
Perform at a temperature of 800 ℃ ~ 1100 ℃ for less than 60 seconds
High temperature short time annealing is preferred. Below 800 ° C
And the effect of impurities on the active state is reduced
There is a risk that the purpose of product activation may not be fully achieved.
On the other hand, when the temperature exceeds 1100 ° C, the diffusion of impurities is remarkable.
This is because the effect of high temperature short time annealing is lost.
It Also, the processing time was set within 60 seconds because it was 60 seconds.
If it exceeds the interval, the diffusion of impurities will progress and it will be out of the desired range.
This is because impurities may reach up to. In addition,
The lower limit of processing time varies depending on the processing temperature.
However, the time for impurities to be fully activated, specifically,
It is set to about 10 seconds.

As the silicon-based gate electrode structure, specifically, a polycide structure in which polysilicon and metal silicide are stacked, a structure in which polysilicon and metal are stacked, a metal such as polysilicon and TiN Structures in which a compound is laminated, and further polysilicon or a
Examples thereof include those having a structure formed of -Si. And in such a silicon-based gate electrode structure,
It is particularly preferable that the impurities are formed by ion implantation. When ion implantation is performed in this way,
This is because the ion-implanted impurities are surely activated by the final high temperature short time annealing. Further, this semiconductor device is an NMO having an N ⁺ type gate electrode.
And S field effect transistor may be <br/> in that a PMOS field effect transistor having a gate electrode of the N ⁺ -type, in which case, the final high-temperature short-time annealing of the, N ⁺ -type gate It is possible to simultaneously activate the impurities and improve the depletion of the electrode and the P ⁺ -type gate electrode.

According to such a method of manufacturing a semiconductor device, the heat treatment step to be performed for activating the impurities is performed in the final step.
Since it was a heat treatment process, impurities were naturally added after this process.
Since there is no active state to affect the heat treatment step, without impurity activated re inactivated moreover since the depletion of the gate electrode is improved, the performance deterioration of the semiconductor device obtained is suppressed .

[0011]

[0012]

[0013]

In the method of manufacturing a semiconductor device according to the third aspect, a step of forming a gate oxide film on the surface of the Si substrate,
On the gate oxide film, the polysilicon film and the gate electrode
And a step of forming an amorphous silicon film,
Impurities are added to the silicon film and the amorphous silicon film.
There is a step of forming an N ⁺ layer and a P ⁺ layer by ion implantation, and a heat treatment step of crystallizing the amorphous silicon.
And heat treatment step of crystallizing the amorphous silicon
And a first heat treatment step performed after the formation of the N ⁺ layer or the P ⁺ layer as a heat treatment step that affects the active state of the impurities.
Of the first heat treatment step, a second heat treatment step performed after the first heat treatment step for a longer time than the first heat treatment step, and a final heat treatment step of the heat treatment steps that affect the active state of the impurities. The third heat treatment step is a heat treatment step for activating the impurities in a shorter time than the second heat treatment step.
And the third heat treatment step is performed at a temperature of 800 ° C to 1100 ° C.
The method for solving the above-mentioned problem was to perform the time within 60 seconds .

Here, the first heat treatment step or the third heat treatment step is performed at a temperature of 800 ° C. to 1100 ° C. for 60 seconds or less at a high temperature for the same reason as in the first aspect of the invention. Short time annealing is preferred, and second
Specifically, the heat treatment step is performed at a temperature of 600 ° C. to 950 ° C. for 10 minutes or more. Sanawa
However, heat treatment below 600 ° C is almost impossible even after long time
This is because the active state of impurities is not affected, and 950
Impurity mutual diffusion occurs when heat treatment at a temperature above ℃ for 10 minutes or more
This is because the device characteristics are deteriorated due to the above-mentioned problems. Further, the silicon-based gate electrode structure is specifically the same as that of the invention according to claim 1 , and the semiconductor device also has an N ⁺ -type gate electrode.
MOS field effect transistor and P ⁺ type gate electrode
And a PMOS field effect transistor having
It can also be applied to so-called Dual Gate type. That
In this case, the N ⁺ type
Impurity activation of the gate electrode and the P ⁺ -type gate electrode,
It is possible to improve depletion at the same time.

According to such a method of manufacturing a semiconductor device, after the first heat treatment step and the second heat treatment step , the final heat treatment step is performed.
Since the third heat treatment step is performed at the same time, even if the gate electrode is once depleted by the second heat treatment step , the third heat treatment step is finally performed.
Since the impurity in the silicon-based gate electrode is activated again by the heat treatment step of 3 , and there is no heat treatment step that influences the active state of the impurity after that, depletion of the gate electrode is improved. Performance deterioration of the semiconductor device is suppressed.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail based on embodiments thereof. 1 (a) to 1 (c) and FIG.
(A)-(c) is a figure for demonstrating the 1st Embodiment of this invention, and this 1st Embodiment carries out this invention by the Single.
This is an example when applied to a method of manufacturing a gate type CMOS circuit.

In this example, first, as shown in FIG. 1A, the field oxide film 2 is formed on the Si substrate 1 by the LOCOS method by the WET oxidation method at 950 ° C., for example. Next, in the region for forming the NMOSFET, P
Ion implantation for forming a buried layer for the purpose of forming a well region and preventing punch through of a transistor, and further ion implantation for adjusting Vth (threshold voltage),
An NMOS channel region 3 is formed on the surface layer of the Si substrate 1. Similarly, in the region for forming the PMOSFET, ion implantation for forming an N well region and for forming a buried layer for the purpose of preventing punch-through of the transistor, and further ion implantation for adjusting Vth are performed.
The PMOS channel region 4 is formed in the surface layer portion.

Next, as shown in FIG. 1B, a gate oxide film 5 having a thickness of 8 nm is formed on the surface of the Si substrate 1 by a thermal oxidation method of heating at 850 ° C. in an H ₂ / O ₂ atmosphere.
Then, for example, SiH ₄ / PH ₃ is used as a source gas, and a-Si doped with phosphorus (P) is deposited by a low pressure CVD method at a deposition temperature of 550 ° C., and a 100 nm thick a-S is deposited.
The i film 6 is formed. Next, for example, WSi _x is deposited on the a-Si film 6 by a low pressure CVD method using WF ₆ / SiH ₄ as a source gas and a deposition temperature of 380 ° C.
A 0 nm WSi _x film 7 is formed. On top of this,
For example, using SiH ₄ / O ₂ as a raw material and depositing SiO ₂ by a CVD method with a deposition temperature of 420 ° C., a thickness of 150 n
An offset oxide film 8 of m is formed. That is, a W polycide wiring layer with an offset oxide film is obtained by such a process.

Next, resist patterning is carried out by a known lithography method, and then an offset oxide film made of SiO _{2 is formed} by anisotropic etching using, for example, a fluorocarbon-based gas with the resist pattern (not shown) obtained as a mask. 8 is a gate electrode pattern. Then, after removing the resist pattern, using the obtained gate electrode pattern as a mask, for example, Cl ₂ /
By anisotropic etching with O ₂ , the WSi _X film 7, a-
The Si film 6 is etched to form a gate electrode pattern, whereby a gate electrode pattern 9 is obtained as shown in FIG. Since the gate electrode pattern 9 thus obtained has the gate electrode pattern made of the a-Si film 6, it has the silicon-based gate electrode structure of the present invention.

Then, using the gate electrode pattern 9 and the field oxide film 2 as a mask, for example, As ⁺ is added to the NMOS channel region 3 at 20 keV, 5 × 10 ¹³ / cm ^2.
Ion implantation is performed under the above conditions to form the NLDD region 10.
Similarly, in the PMOS channel region 4, for example, BF ₂ ⁺
Is ion-implanted under the conditions of ²⁰ keV and 2 × 10 ¹³ / cm ² to form the PLDD region 11. And the Si substrate 1
SiO ₂ having a thickness of 150 n is formed by, for example, low pressure CVD
Then, the SiO ₂ film thus obtained is anisotropically etched to form sidewalls 12 on both sides of the gate electrode pattern 9 as shown in FIG.

Next, for example, As ⁺ is ion-implanted into the NMOS channel region 3 under the conditions of ²⁰ keV and 3 × 10 ¹⁵ / cm ² to form N ⁺ type source / drain regions 13. Similarly, BF ₂ ⁺ is ion-implanted into the PMOS channel region 4 under the conditions of ²⁰ keV and 3 × 10 ¹⁵ / cm ² to form the P ⁺ type source / drain regions 14. Although FIG. 2A shows that the N ⁺ type source / drain regions 13 and the P ⁺ type source / drain regions 14 are formed deeper than the NLDD region 10 and the PLDD region 11, respectively. Since the diffusion process of the implanted impurities is not actually performed, at this stage, as shown in FIG.
Impurities are not deeply diffused as in (a). That is, for the N ⁺ type source / drain regions 13 and the P ⁺ type source / drain regions 14 shown in FIG. 2A, the states obtained after the diffusion process described later are shown for convenience.

[0023] Then, SiO by CVD, for example, a SiH ₄ / O ₂ as a source gas, the deposition temperature and 420 ° C.
₂ or PSG is deposited to form an interlayer insulating film 15 having a thickness of 500 nm as shown in FIG. Subsequently, resist patterning is performed by a known lithography method, and the obtained resist pattern (not shown)
Is used as a mask, and the source / drain region 1 is anisotropically etched by using, for example, a fluorocarbon gas.
A contact hole 16 communicating with 3 and 14 is formed.

Then, through the contact hole 16,
For example, P ⁺ (phosphorus) is formed in the N ⁺ type source / drain region 13.
The 5 × 10 ¹⁵ / cm ² of about implanted similarly BF ₂ ⁺ a 5 × 10 ¹⁵ / cm ² approximately ions are implanted into the source / drain regions of the P ⁺ -type. This ion implantation is called contact implantation, and is performed in order to suppress junction leakage or the like caused by digging the field oxide film or the Si substrate 1 due to etching when forming the contact hole 16. is there.

[0025] Subsequently, as affecting thermal process in an active state of the impurity ion-implanted earlier, 1000 ° C., subjected to 10 seconds high temperature and short time annealing (RTA), forming a CMOS structure and activating the impurity To do. RT here
A is in the present invention are those comprising a heat treatment step of performing a final of affecting heat treatment process in an active state of an impurity, such a RTA, the source / drain regions 13 and 14 as previously described The ion-implanted impurities are diffused / activated to the state shown in FIG. 2A, and the ion-implanted impurities are also diffused / activated through the contact holes 16 so that the impurity diffusion layer 1 is formed as shown in FIG. 2C.
7 and 18 are formed.

Thereafter, a wiring material such as Al is deposited and further patterned, so that a wiring pattern 19 such as a gate, a source and a drain is formed as shown in FIG. 2C.
To obtain a CMOS circuit. It should be noted that the formation of the wiring pattern 19 does not include a heat treatment step that affects the active state of impurities, specifically, a step of performing heat treatment at 700 ° C. or higher. Of course, there is no step of performing heat treatment at 700 ° C. or higher in order to prevent the pattern 19 from melting.

Therefore, in this manufacturing method, after the ion implantation into the contact hole and activation by RTA for 10 seconds at 1000 ° C., a heat treatment at 700 ° C. or higher is performed because it is a wiring process of Al or the like. Therefore, since the activated impurities are not inactivated again, the N ⁺ type source / drain layer 13 (N ⁺ layer) or P ⁺
It is possible to suppress an increase in resistance of the source / drain layer 14 (P ⁺ layer) of the mold and to improve depletion of the gate electrode pattern 9, whereby a high-performance CMOS circuit can be formed.

3A to 3C and 4A to 4C.
FIG. 4 is a diagram for explaining a second embodiment example of the present invention,
This second embodiment is an example of the present invention in which an N ⁺ / P ⁺ dual gate is used.
1 is an example when applied to a method for manufacturing a positive-type CMOS circuit. In this example, first, as in the first embodiment, S
The field oxide film 2 is formed on the i substrate 1 and further Si
An NMOS channel region 3 and a PMOS channel region 4 are formed on the surface layer of the substrate 1, and a gate oxide film 5 is formed on the surface of the Si substrate 1.

Next, for example, using SiH ₄ as a raw material, Poly-Si is deposited by a low pressure CVD method at a deposition temperature of 610 ° C., and as shown in FIG.
The Si film 20 is formed. Subsequently, for example, SiH ₄ is used as a source gas, and a-Si is deposited by a low pressure CVD method at a deposition temperature of 550 ° C., and a thickness of 50 is formed on the Poly-Si film 20.
An a-Si film 21 having a thickness of nm is formed. Then, resist patterning is performed by a known lithography method, and then using the obtained resist pattern (not shown) as a mask, P ⁺ (phosphorus) is added to 10 keV only in the region where the NMOSFET is formed (the region where the NMOS region 3 is formed). 5x
Ions are implanted under the condition of 10 ¹⁵ / cm ² to form an N ⁺ gate region 22 (N ⁺ layer) as shown in FIG. Further, a resist pattern (not shown) obtained in the same manner is used as a mask to form a PMOSFET forming region (PMO).
B ⁺ is 5 keV, 5 × only in the region where the S region 4 is formed)
Ion implantation is performed under the condition of 10 ¹⁵ / cm ² and P ⁺ gate region 2
3 (P ⁺ layer) is formed.

Next, for crystallization of the a-Si film 21,
As the high temperature long-time annealing, heat treatment is performed at 650 ° C. for 10 hours. Then, the high-temperature long-time annealing causes the a-Si film 21 to crystallize, and is made of crystals having a larger grain size than the crystals of the Poly-Si film 20 formed by the CVD method.
The Poly-Si film 21a is formed. Then, following this, RTA under the condition of 1000 ° C. for 10 seconds is performed.
Impurities on the surface of the Si film 21a are diffused into the Poly-Si film 21a, and the Poly-Si film 21a and the Poly-Si film 21a are diffused.
The impurities ion-implanted into the film 20 are activated. That is, this RTA is the first heat treatment step as the heat treatment step that affects the active state of the impurities in the present invention.

Then, for example, WSi _x is deposited on the Poly-Si film 21a by a low pressure CVD method using WF ₆ / SiH ₄ as a source gas and a deposition temperature of 380 ° C. to have a thickness of 7
A 0 nm WSi _x film 24 is formed. On top of this, for example, SiH ₄ / O ₂ is used as a raw material, and the deposition temperature is 420
SiO ₂ is deposited by a CVD method at a temperature of 15 ° C. to a thickness of 15
An offset oxide film 25 of 0 nm is formed. That is,
Through these steps, a W polycide wiring layer with an offset oxide film is obtained as in the first embodiment.

Next, a resist patterning is performed by a known lithography method, and thereafter, an offset oxide film made of SiO _{2 is formed} by anisotropic etching using, for example, a fluorocarbon-based gas with the obtained resist pattern (not shown) as a mask. 25 is a gate electrode pattern. Then, after removing the resist pattern, using the obtained gate electrode pattern as a mask, for example, Cl ₂ /
By anisotropic etching with O ₂ , the WSi _X film 24, Po
The ly-Si film 21a and the Poly-Si film 20 are etched to form a gate electrode pattern.
The N ⁺ -type gate electrode 26a on the side of forming the N ⁺ gate region 22 as shown in (c), also obtain the gate electrode 26b of the P ⁺ -type on the side forming the P ⁺ gate regions 23. In addition,
The gate electrodes 26a and 26b thus obtained are
Since it has a gate electrode pattern composed of the Poly-Si film 21a and the Poly-Si film 20, it has the silicon-based gate electrode structure of the present invention.

Next, with the gate electrodes 26a, 26b and the field oxide film 2 as a mask, for example, As ⁺ is added to the NMOS channel region 3 at 20 keV, 5 × 10 ¹³ /
Ions are implanted under the condition of cm ² to form the NLDD region 27. Similarly, BF ₂ ⁺ is ion-implanted into the PMOS channel region 4 under the conditions of ²⁰ keV and 2 × 10 ¹³ / cm ² to form the PLDD region 28. And Si
SiO ₂ is formed on the substrate 1 to a thickness of 1 by, for example, low pressure CVD.
By depositing to a thickness of 50 nm and further anisotropically etching the obtained SiO ₂ film, sidewalls 29 are formed on both sides of the gate electrodes 26a and 26b as shown in FIG. 4A.

Next, for example, As ⁺ is ion-implanted into the NMOS channel region 3 under the conditions of ²⁰ keV and 3 × 10 ¹⁵ / cm ² to form an N ⁺ type source / drain region 30 (N ⁺ layer). Similarly, in the PMOS channel region 4, for example, B
F ₂ ⁺ is ion-implanted under the conditions of ²⁰ keV and 3 × 10 ¹⁵ / cm ² to form a P ⁺ type source / drain region 31 (P ⁺ layer). Then, in order to activate the impurities in the source / drain regions 30 and 31, high temperature short time annealing (RTA) at 1000 ° C. for 10 seconds is performed to diffuse and activate the impurities in the source / drain regions 30 and 31. CMO
Form an S structure. Note that this RTA is a heat treatment step that affects the active state of impurities in the present invention, and corresponds to the first heat treatment step.

[0035] Then, SiO, for example, by SiH ₄ / O ₂ as a raw material gas, CVD method to 420 ° C. The deposition temperature
₂ or PSG is deposited to form an interlayer insulating film 32 having a thickness of 500 nm as shown in FIG. Subsequently, in order to densify the interlayer insulating film 32, heat treatment is performed at 800 ° C. for 30 minutes as high temperature long-time annealing. Then, although the interlayer insulating film 32 is densified by this high-temperature long-time annealing, the previously activated N ⁺ type gate electrode (N ⁺ layer) 26a and P ⁺ type gate electrode (P ⁺ layer) 26 are activated.
b, N ⁺ type source / drain region (N ⁺ layer) 30, P ⁺
Impurities in the source / drain region (P ⁺ layer) 31 of the p-type become inactive again, depletion occurs in the gate electrodes 26a, 26b, and the source / drain region 30,
At 31, the resistance increases. It should be noted that this high-temperature long-time annealing is performed by the second heat treatment performed after the first heat treatment step in the present invention.
Is the heat treatment step .

Then, resist patterning is performed by a known lithographic method, and then the source / drain regions 30 are formed by anisotropic etching using, for example, a fluorocarbon-based gas with the obtained resist pattern (not shown) as a mask. Contact hole 3 leading to 31
3 is formed. Then, for example, P ⁺ (phosphorus) is ion-implanted into the N ⁺ -type source / drain region 30 through the contact hole 33 at about 5 × 10 ¹⁵ / cm ² , and similarly P ⁺
Type source / drain region 14 with BF ₂ ⁺ of 5 × 10 ¹⁵ /
Ion implantation of about cm ² . In addition, this ion implantation also
Similar to the case of the first embodiment, this is for suppressing the occurrence of junction leak and the like.

Subsequently, as a heat treatment step that affects the active state of the previously ion-implanted impurities, 950 ° C. and 10
A high temperature short time annealing (RTA) under the condition of second is performed to activate the impurities and form a CMOS structure. R here
TA is the final thermal step of the thermal steps that affect the active state of the impurities in the present invention, that is, the final high-temperature short-time anneal.
By A, as described above, the impurities that have been inactivated by the high temperature and long time annealing are reactivated and activated, and the impurities ion-implanted through the contact holes 33 are also diffused and activated. The N ⁺ type source / drain regions 30 and the P ⁺ type source / drain regions 14 obtained by reactivating the impurities in this manner
Has an impurity concentration of 1 × 10 ²⁰ / cm ³ or more.

After that, a wiring material such as Al is deposited and further patterned, so that a wiring pattern 34 such as a gate, a source and a drain is formed as shown in FIG. 4C.
To obtain a CMOS circuit. It should be noted that the formation of the wiring pattern 34 does not include a heat treatment step that influences the active state of impurities as in the first embodiment, specifically, a step of performing heat treatment at 700 ° C. or higher. , After the wiring pattern 34 is formed, the pattern 34
Of course, it does not have a step of performing heat treatment at 700 ° C. or higher in order to prevent the melting of the alloy.

[0039] Thus, in this manufacturing method, although performing several times of high temperature for a short time annealing and high temperature for a long time anneal as affecting thermal treatment process in an active state of the impurity, a heat treatment step performed its final Since the annealing is performed at a high temperature for a short time, the impurities activated by the final RTA are not inactivated again, so that N
The resistance increase of the ⁺ type source / drain layer (N ⁺ layer) 30 and the P ⁺ type source / drain layer (P ⁺ layer) 31 is suppressed, and the N ⁺ type gate electrode (N ⁺ layer) 26a, P is formed. ^{The depletion of the +} type gate electrode (P ⁺ layer) 26b can be improved,
As a result, a high performance CMOS circuit can be formed.

Experimental Example P ⁺ (phosphorus) was ion-implanted into polysilicon on a silicon substrate under the condition of 3 × 10 ¹⁵ / cm ² to form an N ⁺ gate electrode to obtain a MOS structure. Then, this MOS structure has a first condition of 1000 ° C. for 10 seconds .
Perform first RTA (first heat treatment step), further 800
℃, 30 minutes high temperature long time annealing (second heat treatment
Performs a degree), then 950 ℃, for 10 seconds final RTA
(Third heat treatment step) was performed. At this time, the CV characteristics of this MOS structure were examined after each annealing treatment. The obtained results are shown in FIG. From FIG. 5, the first RTA (10
After annealing at 00 ° C for 10 seconds, high temperature long time annealing (8
When performed at 00 ° C. for 30 minutes, the gate electrode is depleted and the capacitance is reduced as compared with after the first RTA. However, it can be seen that by performing the final RTA (950 ° C., 10 seconds) after that, the depletion of the gate electrode is improved and the capacity is recovered.

On the surface layer of the silicon substrate, 20 k As ⁺
An N ⁺ type diffusion layer was formed by ion implantation under the conditions of eV and 3 × 10 ¹⁵ / cm ² . Similarly, BF ₂ ⁺ is 20 keV, 3 ×
Ions were implanted under the condition of 10 ¹⁵ / cm ² to form a P ⁺ type diffusion layer. Then, the silicon substrate is heated to 1000 ° C. for 10
The first RTA (first heat treatment step) under the condition of second second is performed, and further high temperature long-time annealing at 800 ° C. for 30 minutes
(Second heat treatment step) was performed, and then a final RTA (third heat treatment step) was performed at 950 ° C. for 10 seconds. At this time, the sheet resistance of each diffusion layer was examined after each annealing treatment. The obtained results are shown in FIG. From FIG. 6, when the first RTA (1000 ° C., 10 seconds) and then the high temperature long time annealing (800 ° C., 30 minutes) are performed, the impurities are inactivated and the sheet resistance is increased as compared to after the first RTA. To do. However, after that, the final RTA (950 ° C, 10 seconds)
It can be seen that by carrying out the step, the impurities are reactivated and the sheet resistance is lowered to near the original value. (FA in FIG. 6 is an abbreviation for high temperature long time annealing.)

As shown in FIG. 7, PM is deposited on the silicon substrate.
An OS structure was formed. In FIG. 7, reference numeral 40 is a P ⁺ gate, 41 is a P ⁺ diffusion layer, and 42 is an N ⁺ diffusion source (gate). The W / L of this PMOS is 1 μm / 1 μm. Further, the distance between the P ⁺ diffusion layer 41 and the N ⁺ diffusion source 42 was set to d, and this d was changed to obtain a plurality of types of PMOS structures. Annealing treatment was performed on the PMOS having such a structure under the following four conditions. (1) Perform only RTA at 1000 ° C. for 10 seconds. (2) Perform RTA at 1000 ° C. for 10 seconds, then
Annealing is performed at 800 ° C. for 30 minutes at a high temperature for a long time. (3) Perform RTA at 1000 ° C. for 10 seconds, then
Annealing is performed at 850 ° C. for 30 minutes at a high temperature for a long time. (4) Perform RTA at 1000 ° C. for 10 seconds, then
Annealing is performed at 900 ° C. for 30 minutes at a high temperature for a long time. After performing such an annealing process, the P ⁺ diffusion layer 4
The variation of the threshold voltage (Vth) due to the mutual diffusion between 1 and the N ⁺ diffusion source 42 was investigated. The obtained results are shown in FIG. In FIG. 8, the X axis is the distance d between the P ⁺ diffusion layer 41 and the N ⁺ diffusion source 42.

From FIG. 8, it was confirmed that when the post-annealing (high-temperature long-time annealing) at 850 ° C. or higher is performed after the RTA, the Vth fluctuation becomes large. That is, if the N ⁺ diffusion source 42 is located sufficiently far from the P ⁺ diffusion layer 41, or if the N ⁺ diffusion source 42 is absent, FIG.
The original Vth of the PMOS can be obtained as shown in, but N ⁺
When the diffusion source 42 is located at a position that affects the P ⁺ diffusion layer 41, Vth generally fluctuates (V
The absolute value of th will increase). Therefore, as shown in FIG. 8, when the annealing treatment is performed under the conditions (3) and (4), Vth varies (absolute value increases) due to impurity diffusion from the N ⁺ diffusion source 42. You can see that it is closed.

Further, a structure similar to the PMOS structure shown in FIG. 7 was manufactured, and an annealing process was performed on this structure under the following conditions. For the N ⁺ diffusion source 42, P ⁺ (phosphorus)
Is ion-implanted under the conditions of 10 keV, 3 × 10 ¹⁵ / cm ² , and for the P ⁺ diffusion layer 41, B ⁺ is 5 keV, 4
It was formed by ion implantation under the condition of × 10 ¹⁵ / cm ² . (5) Perform only RTA at 1000 ° C. for 10 seconds. (6) Perform RTA at 1000 ° C. for 10 seconds, then
Annealing is performed at 800 ° C. for 30 minutes at a high temperature for a long time. (7) Perform RTA at 1000 ° C. for 10 seconds, then
Annealing is performed at 800 ° C. for 30 minutes at a high temperature for a long time, and then RTA is performed at 950 ° C. for 10 seconds. After performing such an annealing process, the P ⁺ diffusion layer 4
The variation of the threshold voltage (Vth) due to the interdiffusion between 1 and the N ⁺ diffusion source 42 was investigated. The obtained results are shown in FIG.
Shown in.

From FIG. 10, RTA as in the condition (5)
In the case of performing only the RTA, after performing the high temperature long time annealing as in (7),
It can be seen that there is almost no fluctuation in Vth (increase in absolute value). Therefore, according to the manufacturing method of the present invention, resistance increase and gate depletion occur when the final thermal process is a high-temperature long-time anneal of about 800 to 850 ° C. as in the conventional case, and when the temperature exceeds 850 ° C. Vth due to diffusion
In contrast to the fluctuation, the resistance increase is suppressed as described above without causing the fluctuation of Vth due to the mutual diffusion of impurities.
The gate depletion can be improved.

The resistance increase and depletion are 800 to 850.
The longest annealing at ℃ is 1000 ℃, 1
It is considered that the impurities activated by RTA for 0 seconds become supersaturated by the heat treatment at about 800 ° C. (that is, the number of impurity atoms deviating from the lattice point increases), and thus become inactive. That is, when the temperature is lower than this temperature, the impurities do not move (diffuse), and when the temperature is higher than this temperature, the impurities are not in the supersaturated state, so that the inactive state does not occur.

[0047]

As described above, in the method of manufacturing a semiconductor device of the present invention, the final heat treatment step is a heat treatment step for activating the impurities, so that the impurities can be reliably activated. Therefore, even when the N ⁺ gate and the P ⁺ gate are provided, for example, fluctuations in the threshold voltage due to impurity interdiffusion between them and an increase in the depth (Xj) of the diffusion layer, etc. Without inviting
It is possible to suppress an increase in resistance of the ⁺ layer and the P ⁺ layer and achieve low resistance. Further, when the gate electrode is a silicon-based gate electrode, depletion of the gate electrode can be improved. Further, even if resistance increase / gate electrode depletion occurs once by the second heat treatment step, resistance reduction / gate capacitance recovery can be achieved by the third heat treatment step finally performed. Thus, according to the present invention,
MOSF, such as an increase in the depth (Xj) of the diffusion layer and a change in Vth due to impurity interdiffusion between the N ⁺ gate and the P ⁺ gate
The above effect can be achieved without causing deterioration of ET, deterioration of CMOS circuit performance, and the like .

[Brief description of drawings]

1A to 1C are side cross-sectional views of main parts for explaining a first embodiment of the present invention in process order.

2 (a) to 2 (c) are side cross-sectional views of a main part for explaining a step following the step in FIG. 1 in the order of steps in the first embodiment of the present invention.

3 (a) to 3 (c) are side cross-sectional views of relevant parts for explaining the second embodiment of the present invention in the order of steps.

4 (a) to 4 (c) are side cross-sectional views of a main part for explaining the step following the step of FIG. 3 in the order of steps in the second embodiment of the present invention.

FIG. 5 is a graph showing the CV characteristics of the MOS structure after annealing.

FIG. 6 is a diagram showing a relationship between an annealing condition and a sheet resistance of a diffusion layer after an annealing process.

FIG. 7 is a plan view showing a schematic configuration of a PMOS structure used in an experiment.

FIG. 8 is a graph showing a change in threshold voltage (Vth) after annealing the PMOS structure shown in FIG.

FIG. 9 is a graph diagram for explaining a variation in threshold voltage due to mutual diffusion.

FIG. 10 is a graph showing a change in threshold voltage (Vth) due to mutual diffusion between a P ⁺ diffusion layer and an N ⁺ diffusion source after annealing.

FIG. 11 shows N when post-annealing is performed after RTA.
It is a graph which shows the fluctuation | variation of the sheet resistance of a ⁺ diffusion layer and a P ⁺ diffusion layer.

[Explanation of symbols]

1 Si substrate 3 NMOS channel region 4 PMOS channel region 6 a-Si film 9 Gate electrode pattern 10, 27 NLDD region 11, 28 PLDD region 13, 30 N type source / drain region 14, 31 P type source / drain region 15, 32 Interlayer insulating film 16, 33 Contact hole 17, 18 Impurity diffusion layer 20 Poly-Si film 21 a-Si film 22 N ⁺ gate region 23 P ⁺ gate region 26a N ⁺ type gate electrode 26b P ⁺ type gate electrode

Front page continued (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/265 H01L 21/28 H01L 21/8238 H01L 27/092 H01L 29/78

Claims (5)

(57) [Claims] 1. A gate oxide film is formed on the surface of a Si substrate.
Process and phosphorus on the gate oxide film by a low pressure CVD method.
And a WSi _x film is formed on the amorphous silicon film.
Process and patterning the WSi _x film and the amorphous silicon film.
And forming a gate electrode by ion implantation of impurities into the Si substrate to form a source and a drain.
Forming an emission region, and a heat treatment step for activating the impurity, a heat treatment step for activating the impurity, the impure
Of the heat treatment processes that affect the active state of the product,
The heat treatment step is performed at 800 ° C. to activate the impurities.
A method of manufacturing a semiconductor device, which is performed at a temperature of 1100 ° C. for a time of 60 seconds or less. Wherein said semiconductor device is an NMOS field effect transistor having a gate electrode of the N ⁺ type, according to claim 1, wherein those having a PMOS field effect transistor having a gate electrode of the N ⁺ -type Manufacturing method of semiconductor device. 3. A gate oxide film is formed on the surface of a Si substrate.
Process and polysilicon film to be a gate electrode on the gate oxide film
And a step of forming an amorphous silicon film, the polysilicon film and the amorphous silicon film
Process of forming N ⁺ layer and P ⁺ layer by ion implantation of impurities
And extent, and a heat treatment step for crystallizing the amorphous silicon
A first heat treatment step performed after the formation of the N ⁺ layer or the P ⁺ layer as a heat treatment step that affects the active state of the impurities after the heat treatment step of crystallizing the amorphous silicon; After the heat treatment step, a second heat treatment step that is performed for a longer time than the first heat treatment step and a third heat treatment step that is finally performed among the heat treatment steps that affect the active state of the impurities are included. The third heat treatment step is a heat treatment step for activating the impurities, which is performed in a shorter time than the second heat treatment step, and the third heat treatment step is performed at a temperature of 800 ° C. to 1100 ° C. A method of manufacturing a semiconductor device, characterized in that the process is performed for 60 seconds or less. 4. The second heat treatment step is performed at 600 ° C. to 95 ° C.
4. The method of manufacturing a semiconductor device according to claim 3, wherein the method is performed at a temperature of 0 [deg.] C. for 10 minutes or more. 5. The semiconductor device according to claim 3, further comprising an NMOS field effect transistor having an N ⁺ type gate electrode and a PMOS field effect transistor having a P ⁺ type gate electrode. Manufacturing method of semiconductor device.