JP3446424B2 - Method of manufacturing nonvolatile semiconductor memory device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a non-volatile semiconductor memory device having so-called X-type memory cells, and in particular, forming an element isolation region by using a mask pattern which can increase a margin of misalignment with a gate electrode. And a method for manufacturing a nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art Recently, in the field of non-volatile semiconductor memory devices such as mask ROM and flash memory, low voltage,
The demand for higher speed is increasing. On the other hand, there is still a strong demand for cost reduction and large capacity due to high integration, and the memory cell type is selected according to the demand.

For example, in a large-capacity mask ROM, a NAND type cell, a FLAT cell, or the like is adopted as a memory cell type for high integration. In these cell types, the memory transistors can be connected in series to reduce the cell size, but on the other hand, the data is read out through the channel region, which is not suitable for speeding up.

On the other hand, a mask ROM of a high-speed specification mounted on a microcontroller or the like adopts a NOR-type cell format in which data is called through a metal wiring layer to increase the speed. In particular, since a high degree of integration can be achieved to some extent while maintaining a high-speed operation, in recent years, an X-type memory cell among NOR-type memory cells has been increasingly adopted.

FIG. 12 is a schematic plan view in which four X-type memory cells are continuously formed in the step of forming the gate electrode of the conventional mask ROM. In FIG. 12, a memory cell shown by reference numeral 2 and constituting this conventional mask ROM 1 has two selective oxidation regions (LOCOS4) located diagonally and a gate electrode 6 which crosses the selective oxidation regions within the interval of LOCOS4. It is composed of a central memory transistor M ₁₂ which forms a channel region. After the gate electrode 6 is formed, contact holes 8 are provided on both sides of the gate electrode 6 as shown by a two-dot chain line in the figure, and the contact holes 8 are connected to the S / D region of the transistor M ₁₂ via the contact holes 8. The metal wiring layer 10 is formed.

In the whole of FIG. 12 in which four memory cells are made continuous, a substantially triangular L-shape is formed around the central contact hole 8.
The OCOS 4 is formed with its corner portion 4a facing the central contact hole 8. Central contact hole 8
Are four transistors M ₁₁ , M ₁₂ ,
M _21, are shared by M _22, the channel region of the four transistors _{M 11, M 12, M 21} , M 22 are arranged in four directions around the shared contact hole 8. In addition, the metal wiring layer 10 is shared by the halves between the adjacent cells,
Further, since the gate electrode 6 is arranged at an angle of 45 °, the X-type memory cell requires a relatively small cell area.

The metal wiring layer 10 constitutes the bit line (B) in the center of FIG. 12 and the virtual GND lines (Vss) on the left and right sides. In a mask ROM having X-type memory cells, data is read by selectively connecting these to GND.

[0008]

However, such an X
In the process of manufacturing a memory cell, a triangular LOC is used.
After the OS4 was built into the actual device, as shown in FIG. 12, each corner portion 4a was rounded and the top portion was retracted.

In the conventional mask ROM, if the alignment margin is reduced to reduce the cell size, as shown in the figure, when a pattern shift occurs in the vertical direction of the figure in the process of forming the next gate electrode 6. , The edge of the gate electrode 6 easily falls from the LOCOS 4 due to the receding of the top of the LOCOS 4. When this occurs, there is a problem that the leak between the channel regions of the memory transistors (M ₂₁ and M _{22 in the} figure) on both sides of the LOCOS 4 increases, and in severe cases, the channel regions are connected to each other.

FIG. 13 shows a change in the shape of the channel region on an actual device, taking the transistor M ₂₂ as an example, in accordance with the degree of pattern shift when the gate electrode is formed. From the figure, it can be seen that the leak path extends from the channel region as there is no deviation in the figure (A) and as the deviation becomes larger from the figures (B) and (C).

In order to avoid this problem, each LOCO
S4 may be brought close to the shared contact hole 8 or the channel region may be set outward so that the alignment margin is large.
If the LOCOS 4 is brought too close to the contact hole 8, it will overlap with the contact hole 8 and the contact resistance will increase. If the channel region is located outside, the cell size cannot be reduced.

The present invention has been made in view of the above situation, and the element isolation region is formed using a mask pattern for preventing the top from receding, so that the margin of misalignment with the gate electrode can be increased without changing the cell size. An object of the present invention is to provide a method of manufacturing a nonvolatile semiconductor memory device that can be used.

[0013]

The present invention is applied to a non-volatile semiconductor memory device having so-called X type memory cells. That is, in this non-volatile semiconductor memory device, with respect to a transistor constituting a memory cell, four element isolation regions are provided around the contact hole on the source or drain region, and the corners of the element isolation region are directed toward the contact hole. Are formed apart from each other, and the channel regions of four transistors sharing a contact hole are arranged in four directions with the shared contact hole as a center in the space between the adjacent element isolation regions. .

In order to solve the above-mentioned problems of the prior art and to achieve the above object, in the method of manufacturing a nonvolatile semiconductor memory device of the present invention, the recess of the corner portion caused when forming the element isolation region is prevented. In order to prevent this, the mask pattern used for forming the element isolation region is provided with a dummy pattern projecting outward from the corresponding portion on the mask of the corner portion in advance, and the mask pattern is used for element isolation. It is characterized in that a region is formed.

Thus, the corner of the element isolation region can be prevented from receding, and even if the mask alignment margin of the gate electrode with respect to the element isolation region is reduced to reduce the cell size, the edge of the gate electrode falls from the element isolation region. The leak does not increase. That is, in the nonvolatile semiconductor memory device according to this manufacturing method, the misalignment margin of the gate electrode with respect to the element isolation region can be increased, and there is room for higher integration.

The present invention is suitable for reducing the size of memory cells in a so-called ion implantation program type mask ROM. In this case, the source and drain regions are formed for the transistors that form the memory cell,
A metal wiring layer to be connected to the source or drain region through the shared contact hole is formed, and thereafter, programming is performed by selectively introducing impurities into the channel region of a specific transistor by ion implantation. Characterize.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Prior to the description of the present invention,
First, a nonvolatile semiconductor memory device to which the present invention is applied will be briefly described with reference to the drawings. The nonvolatile semiconductor memory device to which the present invention is applied includes a mask ROM and a flash memory whose memory cell system can be a so-called X type. Here, the mask ROM will be described as an example.

As used herein, FIG. 2 is a schematic plan view of an X-type memory cell of a mask ROM to which the present invention is applied, and FIG. 3 is a schematic plan view of four continuous cells. Also,
4 is a schematic cross-sectional structural view of the same cell taken along the line II-II of FIG. 2, FIG. 5 is a schematic cross-sectional structural view of the same cell taken along the line III-III of FIG. 2, and FIG. The transistor connection diagram in FIG. 6B is an equivalent circuit diagram of the same cell.

As shown in FIGS. 2 and 3, this mask ROM
The memory cell 21 forming the memory cell 20 has a selective oxidation region (LO
And COS24), a central memory transistor M ₁₂ which thereby is the isolation, and the contact hole 42a, the source of transistor M ₁₂ or through which the drain region (S
/ D region) metal wiring layer (first metal wiring layer 4)
0) and. In one memory cell 21, a memory transistor is formed along the LOCOS 24 that obliquely passes through the cell, and in all of the four cells, this is arranged in an X shape.
Among the R types, it is particularly called “X type”, and the cell in this case is called “X cell”.

In the whole of FIG. 3 in which four memory cells 21 are continuous, the LOCOS 4 has a substantially triangular shape, and the corner portion 24a is formed in the central contact hole 42a around the central contact hole 42a. It is formed toward. Four transistors M ₁₁ , M ₁₂ , M of each memory cell
₂₁ and M ₂₂ share the central contact hole 42a, and these channel regions are arranged in four directions centering on the shared contact hole 42a. Further, since the first metal wiring layer 30 is shared by adjacent cells by one half and the gate electrode 30 is arranged by being folded at an angle of 45 °, the X cell 21 has a relatively small cell area. Can be small.

In the present embodiment, the shape of the corner portion 24a of the LOCOS 24 is formed in a broad trapezoidal shape. This is to prevent the edge of the gate electrode 30 from falling from the LOCOS 24 due to mask misalignment when the next gate electrode 30 is formed, as will be described later. The mask pattern for producing this shape will be described later.

The first metal wiring layer 40 constitutes the bit line (B) in the center of FIG. 3 and the virtual GND lines (Vss) on the left and right sides. In the X-type mask ROM, these are selectively G
Data is read by connecting to the ND. In addition, the gate electrode 30 is a word line (W ₁ , W ₂ )
Although not shown in the figure, it is possible to make a short circuit in the second metal wiring layer formed after programming.

Next, the sectional structure of the mask ROM 20 will be described with reference to FIGS. As shown in FIGS. 3 and 5, the LOCOS 24 having a substantially square shape (a substantially triangular shape for four memory cells) separates it from the active area 26 in which elements are formed in other areas.
The LOCOS 24 is formed by partially oxidizing the surface of the semiconductor substrate 22.

When the conductivity type of the channel of the memory transistor is n-type (NMOS), the active region 26 is doped with p-type impurities at a relatively low concentration, and p-type (P
In the case of MOS), the opposite n-type impurity is doped to a relatively low concentration. The mask ROM 20 is generally an NMOS
Therefore, in the following embodiments, an NMOS will be described as an example. However, the present invention, even when a PMOS is formed, has a conductivity type including an impurity diffusion layer (S / D region, impurity introduction region) described later. The same can be applied by reversing everything.

As shown in FIGS. 4 and 5, a thin gate oxide film 28 is coated on the surface of the semiconductor substrate 22, and a gate electrode 30 to be word lines (W ₁ , W ₂ ) is formed on the gate oxide film 28. Has been formed. The gate oxide film 28 is composed of, for example, a silicon oxide film formed by a thermal oxidation method. Also,
The gate electrode 30 is composed of, for example, a polysilicon film formed by a CVD method, and conductivity is increased by doping impurities such as phosphorus at a high concentration. In addition, the gate electrode 30
The upper side of the is made low in resistance by laminating a high melting point metal 30a such as WSi _x .

As shown in FIG. 4, a sidewall 32 made of PSG or the like is formed on the side surface of the gate electrode 30. The sidewalls 32 are formed, for example, by anisotropically etching a PSG film formed by the CVD method. The gate electrode 30 is formed on the surface of the semiconductor substrate 22.
L from the edge of the to the outside of the sidewall 32
A shallow junction 34 called DD and a high-concentration deep junction (S /
D regions 36) are formed in self-alignment with the gate electrodes 30 and the sidewalls 32, respectively. These junctions are formed, for example, by performing ion implantation twice before and after forming the sidewall 32 by changing the energy and dose amount, and then performing annealing.

A pair of first metal wiring layers 40, one of which serves as a bit line (B) and the other of which serves as a virtual GND line (Vss), are formed above the left and right sides of the gate electrode 30 with the first interlayer insulating layer 42. Is formed through. The first metal wiring layer 40 is connected to the S / D region 36 via a plug 44 made of W or the like embedded in the contact hole 42a formed in the first interlayer insulating layer 42.

The first metal wiring layer 40 is a main wiring metal film 46.
Antireflection film 48 and barrier metal 50 above and below, respectively.
And has a three-layer laminated structure. The reason for interposing the barrier metal 50 is to improve the high temperature resistance of Al and W, but it can be omitted because the plug is relatively thick. The reason why the antireflection film 48 is provided on the surface side of the main wiring metal film 46 is to open the resist on the upper layer side as a mask for programming ion implantation, as will be described later. This can be omitted in the case where the reflection of is not so large. A second interlayer insulating layer 52 is formed on the first metal wiring layer 40 and planarized.

Although not shown in particular, a second metal wiring for taking out virtual GND lines (Vss), bit lines (B), word lines (W ₁ , W ₂ ) and the like is formed on the second interlayer insulating layer 52. The mask ROM 20 is completed by stacking layers, an overcoat layer, and the like. Next, the mask R of the present invention
A method of manufacturing the OM 20 will be described.

7A and 7B are schematic cross-sectional structural views at the time of ion implantation for programming in the manufacturing process of the present invention. FIG. 7A shows the program side and FIG. 7B shows the non-program side. First, an n-type silicon wafer (for example, specific resistance: 8
˜12 Ωcm) or the like, and a LOCOS 24 (FIG. 3, for separating each cell is prepared on the surface thereof.
5) is formed. To form LOCOS 24,
First, a pad oxide film is formed to a thickness of about 50 nm and an oxidation prevention film such as a silicon nitride film is formed to a thickness of about 100 nm in this order, and these are processed into a predetermined pattern by dry etching.
LOCOS oxidation is performed. The oxidation prevention film is formed by the CVD method or the like. The LOCOS oxidation is performed in a hydrogen combustion atmosphere by, for example, a pyrogenic thermal oxidation method (wet method), and the reaction tube temperature is about 900 to 1100 ° C.
The thickness of the LOCOS oxide film is, for example, 400 to 50.
It is 0 nm.

FIG. 1 is a superposed view of the patterns of the pad oxide film and the oxidation prevention film and the gate electrode pattern. As shown in the figure, the formation pattern 25 of the pad oxide film and the oxidation prevention film (hereinafter, referred to as “LOCOS formation pattern”) has a substantially triangular shape, and the contact hole 42a is formed later. Towards the central space,
The tops 25a are arranged to face each other from all sides. A triangular dummy pattern 25b is formed near each top 25a.
However, they are provided so as to project to the outside on the left and right with a slight distance from each top portion 25a. The dummy pattern 25b is provided to prevent the top portion 25a from moving backward.
The shape of the corner portion 24a of the OS 24 is substantially trapezoidal as described above.

Next, the memory transistor of the memory cell section
And the low voltage transistors in the peripheral circuit
The active region 26 and the low voltage side LOCOS 24
Ion for forming p-well and channel stop
Make each injection. Furthermore, Vth control is applied to the channel area.
Ion implantation for use, for example, mask resist pattern
To do. In the ion implantation for forming the p-well, for example,
Boron ion (B⁺) Energy: 200-400k
eV, dose: 5 × 10¹²~ 2 x 10¹³/ Cm ²Article
To inject. For channel stop, for example, B⁺To
Energy: 100-120 keV, Dose amount: 5 × 1
0¹¹~ 2 x 10¹²/ Cm²Ion implantation under the condition of Vth
For control, for example, B⁺Energy: 20-30ke
V, dose: 1 × 10¹²~ 4 x 10¹²/ Cm²Conditions
Ion implantation with.

Thereafter, for example, in a nitrogen atmosphere at 850 to 900 ° C., after sufficiently annealing, the oxidation prevention film is removed and then the gate oxide film 28 is formed. The gate oxide film 28 is formed in a hydrogen combustion atmosphere (wet type), a thermal oxidation method (dry type), or the like, and the thickness thereof is about 6 to 12 nm.

Next, a polysilicon film or the like, which is a film material of the gate electrode 30, is formed on the gate oxide film 28 by the CVD method or the like, and then a refractory metal film such as WSix is formed. The thickness of the polysilicon film is about 100 nm, and impurities such as phosphorus are introduced to enhance conductivity. The refractory metal film is formed by the CVD method or the sputtering method.
The film is formed to a thickness of about 00 nm. Then, the refractory metal film and the polysilicon film are sequentially etched using the resist having a predetermined pattern as a mask to obtain the gate electrode 30 whose resistance is reduced by the refractory metal 30a.

In the present invention, even if the resist pattern 31 (hereinafter, referred to as "gate electrode forming pattern") at the time of forming the gate electrode 30 is largely deviated to one side as shown in FIG. The dummy pattern 25b provided on the LOCOS formation pattern 25 prevents the shape of the channel region 33 below the gate electrode 30 from being significantly changed from the rectangular shape.

FIGS. 8A to 8C show changes in the shape of the channel region defined by this mask pattern in accordance with the degree of pattern deviation. On the mask pattern, when there is no pattern shift in FIG. 7A, when a slight pattern shift occurs in FIG. 6B, the corners of the channel region once project and a large pattern is formed as shown in FIG. It can be seen that the original rectangle is restored when the shift occurs.

On the other hand, in the actual device on the substrate, as shown in FIG. 9, due to the existence of the dummy pattern 25b,
The left and right corners 24a of the LOCOS 24 bulge in a gentle mountain shape, and the corners 24a are formed in a substantially trapezoidal shape as shown in FIG. Therefore, as the gate electrode formation pattern 31 deviates greatly from FIGS. 9B and 9C, the corners of the channel region are gradually removed. However, the degree of the change is significantly smaller than that in the conventional case of FIG. 13, and the direction of change is not the direction in which the leak path extends. Further, when the pattern shift becomes larger than that in FIG. 9C, a leak path is rapidly formed at a certain place. Therefore, the present invention has an effect of delaying the leak path formation with respect to the pattern shift, that is, increasing the pattern shift margin. I understand that it will be done.

Next, for the memory transistor in the memory cell section and the low voltage transistor in the peripheral circuit, the LDD 34 of low concentration is formed using the formed gate electrode 30 as a mask.
It is formed by an ion implantation method. Then, the sidewall 32 is formed on the sidewall of the gate electrode 30. The sidewall 32 is formed by forming a sidewall material made of, for example, PSG so as to cover the gate electrode 30, and then etching back by RIE or the like from the surface side. Then, using the formed sidewall 32 as a mask,
The high-concentration S / D region 36 is formed by the ion implantation method.

Next, a first interlayer insulating layer 42 such as a silicon oxide film is formed, and a contact hole 42a is formed on each S / D region 36. After that, the contact hole 42 opened
Plug the plug 44 such as W into the CV so as to fill the inside of a.
Barrier metal 50, Al selectively grown by the D method, etc.
The main wiring metal film 46 and the antireflection film 48 are formed in this order. Then, after patterning these first metal wiring layers 40, a second interlayer insulating layer 52 is formed. The second interlayer insulating layer 52 has, for example, SOG for planarization.
(Spin on Glass) and Ozone NSG (Nondoped natural S)
ilicate Glass) is used.

After the formation of the first metal wiring layer 40, the wafer is stocked at the time when the planarization process is completed. Then, the mask ROM 20 is sequentially programmed based on the program data from the customer. As shown in FIG. 7, the program of the mask ROM 20 is performed by introducing an impurity (for example, B ⁺ ) into the channel region of the specific transistor using a mask pattern (resist pattern 54) opened only on the specific transistor. . Since this impurity introduction is performed by high-energy ion implantation, a thick film resist is used, and the film thickness is 1.7 to
It is set in the range of 2.5 μm. Ion implantation conditions for programming are set within a range of energy: 800 to 1200 keV and dose: 1 × 10 ¹³ to 2 × 10 ¹⁴ / cm ² .

As a result of this ion implantation, as shown in FIG. 7, a p-type impurity introduction region 38 is formed in the substrate including the channel region according to the opening width of the resist pattern 54, and programming is performed. In such an ion implantation program type mask ROM, damage is likely to be introduced to the substrate during the ion implantation for programming, and if the element isolation of the LOCOS 24 due to the pattern shift is insufficient as in the conventional case, the occurrence of a leak path is promoted. There is a risk. The present invention is particularly useful in the mask ROM of the ion implantation program system because the element isolation can be sufficiently performed in the present invention.

In this embodiment, the first metal wiring layer 40 is used.
Although the programming is performed from the formed interlayer insulating film 52, if the energy is optimized, the programming can be performed from the interlayer insulating film or the overcoat on the second metal wiring layer. After that, although not particularly shown, after removing the resist pattern 54, a second metal wiring layer and the like are laminated with an interlayer insulating layer interposed therebetween, and finally an overcoat is formed and a pad window is opened to complete the present mask ROM 20.

In the description of the above embodiment, there is no limitation other than the matters specifically mentioned, and various modifications can be made within the scope of the present invention. For example, the dummy pattern 25
The position of b is not limited to that shown in the figure, and for example, a triangular dummy pattern 25b may be provided adjacent to the top portion 25a as shown in FIG. 11 (A). Also,
The shape is not limited to the triangular shape.

At least the LOCOS forming pattern 2
It is necessary that the top portion 25a is hardly retracted when 5 is transferred to the actual device. Ideally, it is desirable that a LOCOS 24 shape close to the setting pattern (triangle in this embodiment) when the dummy pattern 25b is not provided is obtained on the actual device. In order to reduce the change in the channel region of FIG. 9 described above, the dummy pattern 2
It is preferable that the skirting on the actual device by 5b is as gentle as possible.

On the other hand, if there is a margin in the distance from the common contact hole 42a, as shown in FIG.
Far from retracting, on the contrary, the common contact hole 42a
It is also possible to provide a dummy pattern 25c that projects to the side.

[0046]

As described above, according to the method of manufacturing the nonvolatile semiconductor memory device of the present invention, the element isolation region is formed using the mask pattern provided with the dummy pattern to prevent the top recession. Therefore, the margin of misalignment with the gate electrode can be increased without changing the cell size. Further, depending on the shape and position of the dummy pattern, the channel shape is not changed so much and the leak current can be greatly reduced, so that the characteristic variation due to misalignment can be suppressed.

As the misalignment margin can be increased, the size of the memory cell can be reduced, and the nonvolatile semiconductor memory device can be highly integrated.

[Brief description of drawings]

FIG. 1 is a superposed view of a LOCOS forming pattern and a gate electrode forming pattern.

FIG. 2 is a schematic plan view of an X-type memory cell that constitutes the mask ROM of this embodiment.

FIG. 3 is a schematic plan view of four continuous cells.

FIG. 4 is a schematic sectional structural view of the same cell taken along the line II-II of FIG.

5 is a schematic cross-sectional structural view of the same cell taken along the line III-III of FIG.

FIG. 6 (A) is a transistor wiring diagram of the same cell;
(B) is an equivalent circuit diagram of the same cell.

FIG. 7 is a schematic cross-sectional structure diagram at the time of ion implantation for programming in the manufacturing process of a mask ROM of an ion implantation program system as an example of the manufacturing method of the present invention, in which FIG. Indicates the non-program side.

FIG. 8 is a schematic cell plan view showing a shape change of a channel region according to a degree of deviation of a gate electrode formation pattern. 7A shows the case where there is no pattern shift, FIG. 7B shows the case where there is some, and FIG. 7C shows the case where there is a large shift.

FIG. 9 is a cell schematic plan view showing a shape change of the same channel region on an actual device. FIG. 7A shows the case where there is no pattern shift, FIG. 9B shows the case where there is some shift, and FIG.

FIG. 10 is a schematic plan view of four cells showing a case where a gate electrode forming pattern is largely displaced.

FIG. 11 is another example of the form of the dummy pattern.

FIG. 12 is a schematic plan view in which four X-type memory cells are continuous in a gate electrode forming step of a mask ROM of a conventional manufacturing method.

FIG. 13 is a diagram showing an actual device when a conventional manufacturing method is used.
FIG. 6 is a schematic cell plan view showing a change in shape of a channel region according to the degree of displacement of a gate electrode formation pattern. FIG. 7A shows the case where there is no pattern shift, FIG. 9B shows the case where there is some shift, and FIG.

[Explanation of symbols]

20 mask ROM 21 X-type memory cell 22 Semiconductor substrate 24 LOCOS (element isolation region) 24a Corner part 25 LOCOS formation pattern 25a top 25b, 25c dummy pattern 26 Active area 28 Gate oxide film 30 gate electrode 30a refractory metal 32 Sidewall 33 channel area 34 LDD 36 S / D region (source or drain region) 38 Impurity introduction region 40 First metal wiring layer (metal wiring layer) 42 First interlayer insulating layer 42a Shared contact hole 44 plugs 46 Main wiring metal layer 48 Anti-reflection film 50 barrier metal 52 Second interlayer insulating layer 54 resist pattern

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-1-128564 (JP, A) JP-A-7-147334 (JP, A) JP-A-2-214155 (JP, A) JP-A-9- 36334 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 27/112

Claims (2)

(57) [Claims] 1. A transistor constituting a memory cell, wherein four element isolation regions are provided around a contact hole on a source or drain region of the transistor such that a corner portion of the element isolation region faces the contact hole. While being formed, within the space between the adjacent element isolation regions,
A method for manufacturing a non-volatile semiconductor memory device, wherein channel regions of four transistors sharing the contact hole are arranged in four directions centering on the shared contact hole. In order to prevent the receding of the corner portion that occurs, the mask pattern used to form the element isolation region is provided in advance with a dummy pattern protruding outward from the corresponding portion on the mask of the corner portion. A method of manufacturing a non-volatile semiconductor memory device, wherein the element isolation region is formed using a mask pattern. 2. A source / drain region is formed for the transistor forming a memory cell, a metal wiring layer is formed to be connected to the source / drain region through the shared contact hole, and then ion implantation is performed. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein programming is performed by selectively introducing impurities into the channel region of the transistor.