JP3376204B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor layer (hereinafter referred to as an SOI film) provided on a substrate having an SOI (Silicon On Insulator) structure (hereinafter referred to as an SOI substrate). MOSF formed
Regarding ET.

[0002]

2. Description of the Related Art A MOSFET device on an SOI substrate (hereinafter referred to as an SOI device) is excellent in high-speed operation because it has a smaller stray capacitance such as a junction capacitance than a device on a normal bulk silicon semiconductor substrate. Research and development are being actively conducted. MOSFET on SOI substrate
MOSFET on the bulk substrate for controlling the threshold voltage of
Similarly to the above, a method of ion-implanting conductive impurities (channel impurities) into the channel portion is used, and is controlled by the dose amount. However, the SOI device is a bulk device (a MOS device formed on a bulk semiconductor substrate).
It is more strongly influenced by the concentration of channel impurities than semiconductor elements such as T. In particular, the width of the depletion layer directly under the channel formed at the time of channel formation changes depending on the concentration of the channel impurities. It was difficult to achieve both control of value voltage.

In order to solve this, a MOS on an SOI substrate
For the FET, a method of controlling the threshold voltage by utilizing the so-called "back bias effect" of the MOSFET on the SOI substrate, in which the threshold voltage of the MOSFET changes depending on the potential state of the silicon semiconductor substrate under the SOI film, is also attempted. However, since only a uniform potential can be applied to the silicon semiconductor substrate, it is impossible to simultaneously control two or more transistors having different threshold voltages on the circuit by this method. The present invention has been made under such circumstances, and by applying back biases of different potentials to the two or more MOSFETs on the SOI substrate from the silicon semiconductor substrate side under the SOI film, two or more different desired MOSFETs are provided. Provided is a semiconductor device capable of controlling the threshold voltage of the device.

[0004]

The semiconductor device of the present invention comprises:
Each of them is formed on an SOI substrate having a memory cell region and a peripheral circuit region , and is electrically isolated from a surface region of a semiconductor substrate immediately below a MOSFET having two or more different threshold voltages. An impurity diffusion region is formed, and applied voltages of different values are applied to the impurity diffusion region to
It is characterized in that the threshold voltages of two or more different MOSFETs are controlled by the back bias effect. SOI
The impurity diffusion region of the semiconductor substrate directly below the MOSFET formed in the film is formed by ion-implanting a conductive impurity so as to penetrate the SOI film by using an ion implanter capable of applying a high acceleration voltage. To be done. By using the semiconductor device of the present invention for a semiconductor memory, high speed reading / writing can be achieved.

[0005]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. First, FIGS. 1 to 7 and FIG.
A reference example for explaining the present invention will be described with reference to FIG. Figure 1
2A to 2C are cross-sectional views of the semiconductor device, and FIGS. 2 to 7 are cross-sectional views of a manufacturing process of the semiconductor device shown in FIG. The SOI substrate is composed of a semiconductor substrate 1, an insulating film 2 on the semiconductor substrate 1, and a single crystal semiconductor layer 3 (SOI film) formed on the insulating film 2. The SOI film 3 has a plurality of MOSFETs.
(T1, T2) are formed, and these are separated by the oxide film 7 which is an element isolation region. The MOSFET formed in the element region of the SOI film includes a source / drain region 10 arranged at a predetermined distance,
The gate electrode 9 is formed on the source / drain region 10 via the gate oxide film 8. A conductive impurity diffusion region 6 is formed in the surface region of the semiconductor substrate 1 immediately below the MOSFET. MOSFET
An impurity diffusion region 61 is formed immediately below (T1), and M
An impurity diffusion region 62 is formed immediately below the OSFET (T2).

A p-type high-concentration impurity diffusion region 15 serving as a contact region is formed in the semiconductor substrate 1, an n-type impurity diffusion region 141 serving as a contact region is formed in the impurity diffusion region 61, and an impurity diffusion region 62. In this region, an n-type impurity diffusion region 142 to be a contact region is formed. An interlayer insulating film 11 is formed on the MOSFET and the element isolation region so as to cover them. A metal wiring 16 made of aluminum or the like is formed on the interlayer insulating film 11. The metal wiring 16 is electrically connected to the internal contact regions 15, 141, 142 and the source / drain region 10 through a through hole formed through the interlayer insulating film 11 and the element isolation oxide film 7. In the n ⁺ contact region 141 of the impurity diffusion region 61, the metal wiring 161 is formed.
Are electrically connected to the interlayer insulating film 11 through a through hole penetrating the element isolation oxide film 7. MOSFET (T
In the source region of 1), the metal wiring 162 has the interlayer insulating film 1
1 is electrically connected through a through hole.
In the drain region of the MOSFET (T1), metal wiring 1
63 is electrically connected via a through hole penetrating the interlayer insulating film 11. The metal wiring 164 is electrically connected to the p ⁺ contact region 15 of the semiconductor substrate 1 through a through hole penetrating the interlayer insulating film 11 and the element isolation oxide film 7.

In the source region of the MOSFET (T2),
Metal wiring 165 is electrically connected through a through hole penetrating interlayer insulating film 11, and metal wiring 1 is formed in the drain region.
66 is electrically connected through a through hole penetrating the interlayer insulating film 11. Metal wiring 167 is electrically connected to n ⁺ contact region 142 of impurity diffusion region 62 via a through hole penetrating interlayer insulating film 11 and element isolation oxide film 7. The metal wiring 16 is covered and protected by a protective insulating film 17. A terminal for applying a power supply voltage to this wiring is connected to a predetermined metal wiring through a through hole formed in the protective insulating film 17. The first voltage supply means 18 is connected to the metal wiring 161 connected to the impurity diffusion region 61. The second voltage supply means 19 is connected to the metal wiring 167 connected to the impurity diffusion region 62. The third voltage supply means 20 is connected to the metal wiring 164 connected to the high-concentration impurity diffusion region 15 of the semiconductor substrate 1. As shown in FIG.
The element region where the OSFET (T1) is formed is referred to as an A region, and the element region where the MOSFET (T2) is formed is referred to as a B region. In the MOSFET formed on the SOI film having such a structure, the conductive impurity diffusion region 61 in the A region and the conductive impurity diffusion region 62 in the B region of FIG. It is possible to apply a potential. Therefore, for example, 0 V for the silicon semiconductor substrate 1, 1 V for the conductive impurity diffusion region 61 in the A region, and 2 V for the conductive impurity diffusion region in the B region. ,
When different bias potentials are applied to 62), different "back biases" are applied to the MOSFETs formed thereon, so that the MOS in the A region and the MOS in the B region are
In the FET, even though the channel portion is set to have the same impurity concentration, it is possible to set different threshold voltages, and parasitic S
It is possible to prevent deterioration of the characteristics of the OI element (MOSFET).

Next, a method of manufacturing the semiconductor device of FIG. 1 will be described with reference to FIGS. First, for example, the resistance is 4
1 on the p-type silicon semiconductor substrate 1 of about 6 Ωcm
A buried oxide film 2 of SiO ₂ or the like having a thickness of about 00 nm is formed. 200 on the buried oxide film 2
A silicon semiconductor layer (SOI film) 3 having a thickness of about nm is epitaxially grown. The SOI substrate is composed of the semiconductor substrate 1, the buried oxide film 2 and the SOI film 3. Next, the SOI film 3 is oxidized by about 10 nm to form a protective oxide film (SiO ₂ ) 4. After forming the protective oxide film 4, a photoresist is applied thereon and patterned to form a mask 5. Using this mask, conductive impurities, for example, n-type impurities such as phosphorus are added to the semiconductor substrate 1.
Is ion-implanted into the surface region of the. At this time, the ion implanter is one to which a high acceleration voltage of 1 MeV or more is applied, and the acceleration voltage is sufficiently high so that the impurities penetrate the SOI film 3 and the buried oxide film 2 and reach the silicon substrate 1, for example, Ion implantation is performed at a dose of approximately 1 MeV and a dose of approximately 10 ¹² cm ^-2 . In addition, in the region where the impurities are ion-implanted, the impurity diffusion regions immediately below the two or more MOSFETs having different threshold voltages are respectively considered in consideration of the threshold voltage of the MOSFET formed in the SOI film 3. The photoresist is patterned as described above so as to be electrically separated (FIG. 2).

Next, after removing the photoresist mask 5, the conductive impurities are activated by annealing at about 1000 ° C. in an N ₂ atmosphere to diffuse conductive impurities corresponding to the wells of the bulk silicon semiconductor. Area 6 (61, 6
2) is formed (FIG. 3). Next, using the LOCOS method, S
An element isolation oxide film 7 such as SiO ₂ is formed on the OI film 3. It should be noted that it is necessary to open a hole that penetrates the element isolation oxide film 7 and the buried oxide film 2 and reaches the silicon semiconductor substrate 1 at the time of subsequent contact opening. In the element isolation region, it is necessary to completely turn the SOI film 3 into SiO ₂ by oxidation (FIG. 4). Next, ion implantation is performed on the channel portion of the MOSFET formation region to adjust the threshold voltage. Next, after removing the protective oxide film 4, a gate oxide film (SiO ₂ ) is formed on the surface of the SOI film 3 by thermal oxidation or the like.
8 is formed. Then, a polysilicon film doped with phosphorus is deposited and patterned to form a gate electrode 9 on the gate oxide film 8. After forming the gate electrode 9,
Using this as a mask, n-type impurities, such as As, are used for SOI.
Ions are implanted on the entire surface of the film 3 and activation annealing is performed to
A type source / drain region 10 is formed to form a MOSFET. A MOSFET is formed on the impurity diffusion region 61.
(T1) is formed, and MO is formed on the impurity diffusion region 62.
The SFET (T2) is formed (see FIGS. 5 and 16).

Next, the interlayer insulating film 11 made of SiO ₂ or the like is formed on the S
It is deposited on the OI film 3 and the element isolation oxide film 7. Then, a photoresist is applied on the interlayer insulating film 11, and this is patterned to form a mask 12. According to the mask 12, the interlayer insulating film 11 and the element isolation oxide film 7 are etched by RIE (Reactive Ion Etching) or the like to form a plurality of contact holes in predetermined regions. These contact holes are opened so as to reach the impurity diffusion region 6, the main surface of the semiconductor substrate 1 and the source / drain regions 10, respectively (FIG. 6). Next, after removing the mask 12, a photoresist is applied again on the interlayer insulating film 11, and this is patterned to form a mask 13. The mask 13 is formed on the main surface of the semiconductor substrate 1 and the source / source.
The contact hole where the drain region 10 is exposed is covered, and the contact hole where the impurity diffusion region 6 is exposed is not covered. An n-type impurity such as phosphorus (P) is ion-implanted into the contact hole where the impurity diffusion region 6 is exposed, the mask is removed, and then activation annealing is performed.
N ⁺ high-concentration impurity diffusion regions 141 and 142 are formed in the impurity diffusion regions 61 and 62. By forming this high-concentration impurity diffusion region, the contact resistance between the metal wiring and the impurity diffusion region 6 is reduced (FIG. 7).

Next, a mask (not shown) is formed by patterning the photoresist so that the contact hole exposing the semiconductor substrate 1 is exposed and the other contact holes are covered.
To form. A p-type impurity, for example, boron (B) is ion-implanted through this mask, the photoresist is removed thereafter, and activation annealing is performed to form the p ⁺ high-concentration impurity diffusion region 15. Next, an aluminum film is deposited on the interlayer insulating film 11. Then, the interlayer insulating film 1 is formed by using a patterned photoresist (not shown).
1 is etched, and metal wiring 161 connected to the impurity diffusion region 61, metal wirings 162, 163, 165, 166 connected to the source / drain regions 10, and metal wiring 164 connected to the high-concentration impurity diffusion region 15. And a metal wiring 167 connected to the impurity diffusion region 61, respectively. Next, a protective insulating film 17 such as SiO ₂ is deposited so as to cover and protect these metal wirings. After this,
A contact hole with the metal wiring is opened in the protective insulating film 17,
First voltage supply means 18 connected to the metal wiring 161;
The second voltage supply means 19 connected to the metal wiring 167 and the third voltage supply means 20 connected to the metal wiring 164.
Are connected to complete the semiconductor device (FIG. 1).
FIG. 16 is a schematic plan view of FIG. S of the semiconductor substrate 1
An n-channel MOSFET (T1, T2) is formed on the OI film so as to be surrounded by the field oxide film 7, and the n-type impurity diffusion regions 61, 62 of the impurity diffusion region 6 are formed immediately below the n-channel MOSFET (T1, T2).
Are formed in the surface region of the semiconductor substrate 1.

In the semiconductor device of this reference example, since the impurity diffusion region 61 in the A region and the impurity diffusion region 62 in the B region of FIG. 1 are electrically separated, it is possible to apply their own potentials. become. Therefore, for example, 0 V (V0) in the silicon semiconductor substrate 1, 1 V (V1) in the impurity diffusion region 61 in the A region, and 2 V (V2) in the impurity diffusion region 62 in the B region. If different bias potentials are applied to the MOSFETs, different "back biases" are applied to the MOSFETs formed on the MOSFETs.
It is possible to set different threshold voltages (Vth) between T (T1) and MOSFET (T2) in the B region even though the channel portions are set to the same impurity concentration. Therefore, parasitic characteristic deterioration of the SOI element (MOSFET) due to a change in channel impurity concentration can be prevented. To apply the present invention, when the silicon semiconductor substrate 1 is n-type and the impurity diffusion region 6 is p-type,
Silicon semiconductor substrate 1 in which the conductive impurity diffusion regions of the A and B regions have different conductivity types, one is n type and the other is p type
The bias potential of the impurity diffusion regions of the A and B regions may be set to a potential state in which no forward current is generated between the impurity diffusion region and the silicon substrate.

Next, the present invention will be described with reference to FIG.
A consideration example will be described. The figure is a cross-sectional view of a semiconductor device. S
The interlayer insulating film, protective insulating film, metal wiring, etc. formed on the OI substrate are omitted. The SOI substrate is composed of a p-type silicon semiconductor substrate 1, an insulating film 2 such as SiO ₂ on the semiconductor substrate 1, and a single crystal semiconductor layer 3 (SOI film) formed on the insulating film 2. . A plurality of MOSFETs (T2, T3) are formed on the SOI film 3, and these are isolated by the field oxide film 7. MOSF formed in the element region of the SOI film
ET (T2) is an n-type source / drain region 10 and a source / drain region 10 which are arranged with a predetermined distance.
It is composed of a gate electrode 9 made of polysilicon or the like formed on the space between the gate oxide films 8. This MO
A conductive n-type impurity diffusion region 62 is formed in the surface region of the semiconductor substrate 1 immediately below the region where the SFET is formed. The MOSFET (T3) is formed between the p-type source / drain region 14 formed at a predetermined distance in the SOI film 3 and the source / drain region 14 via the gate oxide film 8. The gate electrode 91 is made of polysilicon or the like. A conductive n-type impurity diffusion region 63 is formed in the surface region of the semiconductor substrate 1 immediately below the region where the MOSFET is formed, and a p-type impurity diffusion region 64 is formed in the impurity diffusion region 63.

The first voltage supply means 21 is connected to the p-type impurity diffusion region 64. n-type impurity diffusion region 6
A second voltage supply means 19 is connected to 2. Third voltage supply means 20 is connected to the semiconductor substrate 1. The fourth voltage supply means 22 is connected to the n-type impurity diffusion region 63, thereby stabilizing the potential of this region. In both MOSFETs, the threshold voltage can be set freely, and it is possible to prevent the characteristic deterioration of the SOI element such as the parasitic MOSFET due to the change of the channel impurity concentration. Further, in this embodiment, a p-channel MOSFET (T3) is provided, and the p-type impurity diffusion region 64 is provided immediately below the MOSFET (T3).
Are arranged so as to face each other. That is, the impurity diffusion regions formed in the semiconductor substrate are different in conductivity type from one of n type and the other of p type, but the bias potential applied to the semiconductor substrate 1 and the impurity diffusion regions 62, 64 from the voltage supply means. Is set to a potential state such that no forward current is generated between the impurity diffusion region and the semiconductor substrate, the threshold voltage (Vth) of these MOSFETs can be appropriately lowered.

Next, referring to FIGS. 9 and 10, the present invention will be described.
The voltage supplied by the voltage supply means used will be described. FIG. 9 shows the voltage supplied to the voltage supply means, and FIG.
Shows the type of voltage supplied to the semiconductor substrate shown in FIG. In the case of FIG. 9A, the MOSFET (T
The voltage V1 supplied by the voltage supply means 18 on the side 1) is VDD
The voltage V2 supplied by the voltage supply means 19 on the MOSFET (T2) side is the low potential power supply VSS. Figure 9
In the case of (b), the voltages V1 and V2 are both VBB. In the case of FIG. 9C, the voltages V1 and V2 are VSS and V
It is supplied by selecting one of BB. In the case of FIG. 9D, the voltages V1 and V2 are supplied by selecting one of VSS, VDD and VBB. In the case of FIG. 9 (e), the voltage V1,
V2 is supplied by selecting any one of VSS, VDD, VBL and VBB. FIG. 10 is a characteristic diagram showing the relationship between the internal power supply voltage such as VSS, VDD, VBB, VBL, and Vpp and the external power supply voltage VCC, where the vertical axis represents the internal power supply voltage and the horizontal axis represents the external power supply voltage. . The schematic diagram of FIG. 11 shows a specific magnitude of the power supply voltage and a method of forming the same. These power supply voltages are formed based on the external power supply voltages Vcc and GND. If Vcc is 3 to 3.5V, Vpp is 5V, VDD
Is 3V and VBL is 1.5V. Also, VSS is 0
V and VBB are -2V.

Next, an embodiment of the first invention in which the present invention is applied to a semiconductor memory will be described with reference to FIGS. FIG. 12 is a schematic sectional view of a semiconductor memory such as DRAM. In this semiconductor memory, the impurity diffusion region (well) formed in the surface region of the semiconductor substrate for setting the threshold voltage of the MOSFET by utilizing the back bias effect is common in the memory cell region in which the memory cell array is formed. It has become a region. In the cell region formed on the p-type semiconductor substrate 1, MOSFETs (T1, T
2 and T3), a common n-type impurity diffusion region 66 is formed, and each MOSFET (T4, T5,
N-type impurity diffusion regions 67, 68, 69 for setting the threshold voltage are formed in each of T6). The voltage supply means 20 for supplying the voltage V0 to the semiconductor substrate 1 and the voltage supply means 23 for supplying the voltage V1 to the impurity diffusion region 66.
And a voltage V to the impurity diffusion regions 67, 68 and 69, respectively.
2, voltage supply means 24, 25, 2 for supplying V3, V4
6 is formed. The impurity diffusion region formed in the semiconductor substrate has a bias potential applied to the semiconductor substrate 1 and the impurity diffusion region from the voltage supply means such that no forward current is generated between the impurity diffusion region and the semiconductor substrate. If set to the state, the threshold voltage (V
th) can be lowered.

Since the memory cells in the cell region have the same operating voltage, it is not necessary to form an impurity diffusion region for each cell.
The memory size can be reduced by using the common impurity diffusion region. If the threshold voltage (Vth cell) of the MOSFET in the cell region is made larger than the threshold voltage (Vth periphery) of the MOSFET in the peripheral circuit region (| Vth cell |
> | Vth periphery |), the data storage property of the cell is improved and the speedup of the processing by the peripheral circuit is improved. Figure 13
It is a schematic sectional drawing of semiconductor memories, such as DRAM. This semiconductor memory utilizes the back bias effect to achieve MO
The impurity diffusion region (well) formed in the surface region of the semiconductor substrate for setting the threshold voltage of the SFET is not formed in the cell region. MOSFETs (T1, T2, T3) are formed in the cell region where the p-type semiconductor substrate 1 is formed, and each MOSFET (T4, T3) is formed in the peripheral circuit region.
5, T6), n-type impurity diffusion regions 67, 68, 69 for setting the threshold voltage are formed. Voltages V2 and V are applied to the voltage supply means 20 for supplying the voltage V0 to the semiconductor substrate 1 and the impurity diffusion regions 67, 68 and 69, respectively.
Voltage supply means 24, 25, 26 for supplying 3, V4 are formed.

In the impurity diffusion region formed in the semiconductor substrate, the bias potential applied from the voltage supply means to the semiconductor substrate 1 and the impurity diffusion region does not generate a forward current between the impurity diffusion region and the semiconductor substrate. By setting such a potential state, the threshold voltage (Vth) of the MOSFET can be lowered. Since the memory cells in the cell region have the same operating voltage and it is not necessary to lower the threshold voltage of the cell region, it is not necessary to form the impurity diffusion region and the memory size can be reduced. MOSF in cell area
Set the threshold voltage (Vth cell) of ET to MO in the peripheral circuit area.
When the voltage is higher than the threshold voltage (around Vth) of the SFET (| Vth cell |> | Vth around |), the data storage property of the cell is improved and the processing speed by the peripheral circuit is improved.

Next, a fourth embodiment of the present invention in which the present invention is applied to a peripheral circuit such as a circuit for selecting a memory cell of a semiconductor memory will be described with reference to FIGS . 14 and 5 . Figure 1
4 is a word line WL (WL1, WL2) and a bit line B
Connected to cells connected to L and / BL, a sense amplifier connected to a bit line, and a sense amplifier (S / A),
An input / output line (DQ, / DQ) is a cell selection circuit having a column decoder output CSL connected via an input / output gate (DQ gate), and a sense amplifier (DQS / A) is provided in the input / output line. It is connected.

A voltage supply means 27 is connected to the input / output gate.
Are connected. The voltage supply means 27 applies a bias potential to the impurity diffusion region to the impurity diffusion region (not shown) in the surface region of the semiconductor substrate formed immediately below the pair of n-channel MOSFETs forming the input / output gate. A predetermined voltage set to a potential state where no forward current is generated between the semiconductor substrate and the semiconductor substrate is applied. By applying a predetermined voltage, the threshold voltage (V
th) can be lowered, and the sense amplifier (DQS / A) connected to the input / output line controlled by the input / output gate can be speeded up by appropriately changing the threshold voltage of the MOSFET. The power supply voltage supplied by this voltage supply means is V
pp, VDD, VBL, VSS, etc.

FIG. 15 shows a row system circuit of the same kind as that of FIG. 14, but since it is used for a VRAM or the like, a sense amplifier (S / A) is used.
In addition, a CMOS flip-flop is further provided as a register (TR) such as a temporary register.
The temporary register (TR) is a pair of p-channel MO.
It is composed of an SFET 30 and a pair of n-channel MOSFETs 31. In these MOSFETs 30 and 31,
The voltage supply means 28 and 29 are connected.

The voltage supply means 28 and 29 are MOSFETs.
A bias potential to the impurity diffusion region (not shown) in the surface region of the semiconductor substrate formed immediately below the semiconductor substrate is set to a potential state in which no forward current is generated between the impurity diffusion region and the semiconductor substrate. The predetermined voltage is applied. The threshold voltage (Vth) of the MOSFET can be lowered by applying a predetermined voltage. This temporary register has a mode in which data is held internally and a mode in which data is transferred from outside to inside. The two modes are difficult to be compatible with each other, and it is difficult to transfer if it is easy to hold, and difficult to hold if they are easy to transfer.

According to the embodiment of the present invention, the compatibility is achieved by changing the threshold voltage of the MOSFET of the sense amplifier in the data transfer mode and the data holding mode. That is, the absolute value of the threshold voltage is small in the data holding mode, and the absolute value of the threshold voltage is large in the transfer mode. Based on the above, the voltage supplied from the voltage supply means 28 to the p-type impurity diffusion region formed in the semiconductor substrate immediately below the p-channel MOSFET 30 is VSS, VD in the holding mode.
Low voltages such as D and VBL are suitable, and high potential voltages such as Vpp and VDD are suitable in the transfer mode. The voltage supplied from the voltage supply means 29 to the n-type impurity diffusion region formed on the semiconductor substrate immediately below the n-channel MOSFET 31 is Vpp, VDD, VBL, V in the holding mode.
A high voltage such as SS is suitable, and a low potential voltage such as VSS or VBB is suitable in the transfer mode. Different supply voltage types depending on the above modes are shown in the following table (Table 1).

[0024]

[Table 1]

This temporary register can be applied not only to the VRAM application but also to any register whose mode can be changed.

[0026]

In the plurality of MOSFETs on the SOI film having the above-described structure, the conductive impurity diffusion regions are electrically isolated from each other, so that it is possible to apply a unique potential to each. Therefore, if different bias potentials are applied to the respective conductive impurity diffusion regions,
Since different "back biases" are applied to the MOSFETs formed thereon, these M
The OSFET can set different threshold voltages even if the channel portions are set to have the same impurity concentration, and the parasitic SOI caused by the change in the channel impurity concentration.
It is possible to prevent deterioration of the characteristics of the MOSFET on the film. Further, by applying the present invention to a semiconductor memory, it is possible to obtain a semiconductor memory excellent in both the data holding mode and the data transfer mode.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a semiconductor device according to a reference example .

FIG. 2 is a sectional view of a step of manufacturing the semiconductor device of FIG.

FIG. 3 is a sectional view of a step of manufacturing the semiconductor device of FIG.

FIG. 4 is a sectional view of a step of manufacturing the semiconductor device of FIG.

5A to 5C are cross-sectional views of manufacturing steps of the semiconductor device of FIG.

FIG. 6 is a sectional view of a step of manufacturing the semiconductor device of FIG.

FIG. 7 is a sectional view of a step of manufacturing the semiconductor device of FIG.

FIG. 8 is a sectional view of a semiconductor device of a reference example .

FIG. 9 is a schematic diagram of voltage supply means of the semiconductor device of the present invention.

FIG. 10 is a characteristic diagram showing a relationship between an internal power supply voltage and an external power supply voltage.

FIG. 11 is a schematic diagram showing the relationship of voltages supplied by the voltage supply means of the present invention.

FIG. 12 is a cross-sectional view of a semiconductor device of the present invention.

FIG. 13 is a cross-sectional view of a semiconductor device of the present invention.

FIG. 14 is a system circuit diagram of a semiconductor memory to which the present invention is applied .

FIG. 15 is a system circuit diagram of a semiconductor memory to which the present invention is applied .

16 is a schematic plan view of the semiconductor substrate shown in FIG.

[Explanation of reference numerals] 1 ... Silicon substrate, 2 ... Buried oxide film,
3 ... SOI film, 4 ... Protective oxide film, 5, 1
2, 13 ... Photoresist, 6, 61, 62,
63, 64, 66, 67, 68, 69 ... Impurity diffusion region, 7 ... Element isolation oxide film (field oxide film),
8 ... Gate oxide film, 9, 91 ... Gate electrode, 10, 14 ... Source / drain region, 11
... Interlayer insulating film, 15 ... p ⁺ diffusion region,
16, 161, 162, 163, 164, 165, 16
6 ... Metal wiring, 17 ... Protective insulating film, 18,
19, 20, 21, 22, 23, 24, 25, 26, 2
7, 28, 29 ... Voltage supply means, 30 ... P-channel MOSFET, 31 ... N-channel MOSFE
T, 141, 142 ... N ⁺ diffusion regions.

Front page continued (51) Int.Cl. ⁷ identification code FI H01L 27/10 681F (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 27/108 H01L 21/8242 H01L 27 / 08 H01L 21/8234

Claims (6)

(57) [Claims] 1. A semiconductor substrate, an insulating film formed on the semiconductor substrate, a semiconductor film formed on the insulating film, a plurality of MOSFETs formed on the semiconductor film, and each of the MOSFETs formed. the right under the area being provided with an impurity diffusion region formed in the semiconductor substrate, wherein the impurity diffusion regions are electrically isolated from each other, 且
One bias potential are applied, the semiconductor film, main
This memory cell has a memory cell area and a peripheral circuit area.
The plurality of MOSFETs in the region are common to the impurity diffusion.
A plurality of MOSFs in the peripheral circuit area
Each ET has the individual impurity diffusion region.
Wherein a that. 2. A semiconductor substrate, an insulating film formed on the semiconductor substrate, a semiconductor film formed on the insulating film, a plurality of MOSFETs formed on the semiconductor film, and the MOSFETs are formed. The area directly below the area
An impurity diffusion region formed in the semiconductor substrate, wherein the impurity diffusion regions are electrically isolated from each other, and
Bias voltage is applied, the semiconductor film is
A memory cell region and a peripheral circuit region,
Of the impurity in each of the plurality of MOSFETs in the region.
A semiconductor device having a dispersed region formed therein . 3. A semiconductor device according to claim 1 or claim 2, wherein said semiconductor substrate of said impurity diffused each of the domain voltage supply means is connected. 4. The impurity diffusion region of the memory cell region
The absolute value of the threshold voltage of the MOSFET on the range
From the absolute value of the threshold voltage of the MOSFET on the circuit area
The size is increased according to claim 1 or claim 3.
Mounted semiconductor device. 5. A sensor for reading data from the memory cell.
A flip-flop that has an amplifier and constitutes this sense amplifier
When the flop is in hold mode, this flip-flop
The absolute value of the threshold voltage of the MOSFET
In the comb and transfer mode, the threshold of the MOSFET is
2. The absolute value of the value voltage is increased, as claimed in claim 1.
The semiconductor device according to claim 3 . 6. A sense amplifier for reading data from the memory cell is connected to a temporary register having the voltage supply means, and when a flip-flop forming the temporary register is in a transfer mode, a MOSFET forming the flip-flop is connected. When the impurity diffusion region is p-type, the voltage supply means supplies a higher voltage to the p-type impurity diffusion region than in the holding mode, and when the impurity diffusion region is n-type, the voltage supply means 5. The semiconductor device according to claim 1, wherein a voltage lower than that in the holding mode is supplied to the n-type impurity diffusion region.