JP3359063B2 - Solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device, and more particularly to a solid-state image pickup device comprising a random reset circuit, a random sample circuit and a random access circuit, and a reset operation for each pixel.
The present invention relates to a solid-state imaging device that performs a sample-hold operation and an access operation.

[0002]

2. Description of the Related Art FIG. 25 is a schematic configuration diagram showing an example of this type of solid-state imaging device. In the figure, 1 is the H (horizontal) direction and V
An imaging region having a plurality of pixels arranged in a (vertical) direction, 2 is one pixel constituting the imaging region 1, 3, 4 and 5 are H-direction decoders of a random access circuit, a random reset circuit and a random sample circuit, respectively. , 6 are H-direction address lines, 7, 8, and 9 are V-direction decoders of a random access circuit, a random reset circuit and a random sample circuit, respectively, 10 is a V-direction address line,
11 is a data line, 12 is an output circuit, 13 is an output terminal of a solid-state imaging device, 14 is a control line of an H-direction decoder, and 15 is V
This is a control line of the direction decoder.

FIG. 26 is a diagram showing a specific circuit configuration of the pixel 2, wherein D1 and C1 are photodiodes and storage capacitors which are photoelectric conversion elements, and T1 is a reset transistor for resetting the photodiode D1. , T
2. T3 is a source follower circuit in the first stage, T4 is a sample transistor, C2 is a sample capacitor, T5 and T6 are source follower circuits in the second stage, and T7 is a V-direction access path transistor whose gate is connected to a V-direction access address line. , T8 is an H-direction access pass transistor whose gate is connected to an H-direction access address line, T9 is a V-direction reset pass transistor whose gate is connected to a V-direction reset address line, and T10 is a gate connected to an H-direction reset address line. H-direction reset pass transistor, T11 is a V-direction sample pass transistor having a gate connected to a V-direction sample address line, T12 is an H-direction sample pass transistor whose gate is connected to an H-direction sample address line, and 16 is a data line. Output terminal of the pixel connected to 11 A.

In the above pixel 2, first, an H-direction reset pulse φHr and a V-direction reset pulse φVr are applied, and the H-direction reset pass transistors T10 and V
The direction reset pass transistor T9 is turned on. As a result, the reset transistor T1 is turned on, and the charge stored in the storage capacitor C1 is swept out. Next, the reset transistor T1 is turned off, the photodiode D1 is exposed as much as necessary, and the charge is stored in the storage capacitor C1. At this time, the source follower circuit T2
Since the charge amount is converted to a voltage value by T3, H
Direction sample pulse φHs and V direction sample pulse φ
Vs is applied, and the H-direction sample pass transistor T1
By turning on the 2 and V direction sample pass transistors T11, the sample transistor T4 is turned on, and the voltage value is held in the sample capacitor C2. Thereafter, the sample transistor T4 is turned off. The voltage value held in the sample capacitor C2 is held until the sample transistor T4 is turned on again by the sample pulse. The voltage value held in the sample capacitor C2 is applied to the output terminal of the pixel by applying the H-direction access pulse φHa and the V-direction access pulse φVa and turning on the H-direction access pass transistor T8 and the V-direction access pass transistor T7. 16 is output. The output voltage value is output from the solid-state imaging device as an image signal through the data line 11, the output circuit 12, and the output terminal 13 of the solid-state imaging device.

FIG. 27 is a block diagram showing an example of a solid-state imaging device using the solid-state imaging device of FIG. 27, reference numeral 17 denotes a solid-state imaging device, 18 denotes a comparator, 19 denotes a control signal generator, 20 denotes a shutter and an aperture provided as means for adjusting an exposure amount, 21 denotes an address memory, and 22 denotes an image signal line. It is.

Next, the operation of the conventional device will be described. First, by operating the random reset circuit of the solid-state imaging device 17, the charges of the photodiodes D1 and the storage capacitors C1 of all the pixels are reset in a predetermined order, and the first exposure is performed under a certain exposure condition. When the exposure is completed, the charge stored in the photodiodes D1 and the storage capacitors C1 of all the pixels is converted into a voltage by operating the random sampling circuit, and sampled and held in a predetermined order. Then
An image signal in which all pixels are sampled and held by operating the random access circuit is read out in a predetermined order,
Output from the solid-state imaging device 17. On the other hand, the comparator 18 receives a predetermined reference signal from the control signal generator 19 and compares it with the image signal. The comparison result is returned to the control signal generator 19.

Here, an operation when a predetermined reference signal is set low so that a dark portion can be detected will be described. When the control signal generator 19 determines that the signal currently being compared is lower than the predetermined reference signal and that the second exposure is necessary, the address of the pixel is stored in the address memory 21. At this time, the control signal generator 19
The second exposure condition is calculated from the information sent from step 8. When the comparison of the image signals of all the pixels is completed, the pixels stored in the address memory 21 are reset, and the second exposure is started under the exposure conditions calculated by the control signal generator 19. In the second exposure, the exposure amount is increased by lengthening the exposure time or adjusting the shutter and the aperture 20. Next, the pixel signals stored in the address memory 21 are sampled and held. Then, the signals of all the pixels are read out in a predetermined order and output from the solid-state imaging device 17. This pixel signal is output to a signal processing circuit or the like through the image signal line 22. As described above, since the sensitivity of a dark part can be increased, the dynamic range can be expanded. Of course, it is also possible to set a predetermined reference signal high so that a bright portion can be detected.

In order to detect the bright portion, the exposure time is reduced at the time of the second exposure, or the shutter and the aperture 20 are adjusted to reduce the exposure amount. As a result, it is possible to prevent a bright portion from being saturated and flying white, and to expand the dynamic range. Further, since the same pixel does not become a bright portion and a dark portion at the same time, the reference signal of the low setting and the reference signal of the high setting are sent from the control signal generator 19 to the comparator 18 so that the bright portion and the dark portion can be compared. A determination can be made. Since the second exposure condition can be determined for each of these determinations, the dynamic range of both the bright part and the dark part can be expanded.

[0009]

However, the above-described conventional solid-state imaging device has an advantage of expanding dynamics, but has a disadvantage in that pixels for designating a pixel in each of a random reset circuit, a random sample circuit, and a random access circuit. Since it is necessary to provide the H-direction decoder and the V-direction decoder, there has been a problem that the circuit configuration is complicated and the size of the solid-state imaging device is increased.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to provide a solid-state imaging device capable of simplifying a circuit scale and expanding a dynamic range. is there.

[0011]

SUMMARY OF THE INVENTION An object of the present invention is to have a plurality of pixels arranged in a horizontal direction and a vertical direction, each of which has a photoelectric conversion element, and sweeps out electric charges accumulated in the photoelectric conversion element. Reset switch, a sample-and-hold circuit for sampling and holding the charge as a signal, a random reset circuit for driving a reset switch of a specified pixel, and a sample-and-hold circuit for driving a signal of a specified pixel In a solid-state imaging device including a random sample circuit for sample-holding and a random access circuit for reading a signal of the sample-hold circuit of a designated pixel, the random reset circuit and the random access circuit may include Circuit for specifying address and vertical address Each circuit is achieved by the solid-state imaging device, characterized in that the common.

Another object of the present invention is to have a plurality of pixels arranged in a horizontal direction and a vertical direction, wherein each pixel has a photoelectric conversion element, a reset switch for sweeping out the electric charge accumulated in the photoelectric conversion element, A sample and hold circuit for sampling and holding the charge as a signal, a random reset circuit for driving a reset switch of a designated pixel, and a sample and hold circuit for sampling and holding a signal of a designated pixel in the sample and hold circuit A random sample circuit, and a solid-state imaging device including a random access circuit for reading a signal of a sample and hold circuit of a specified pixel, wherein the random reset circuit, the random sample circuit and the random access circuit, Specify the circuit and vertical address to specify And a switch element for operating a random reset circuit, a random sample circuit, and a random access circuit of a designated pixel, and a random reset circuit and a random access circuit among the switch elements. This is achieved by a solid-state imaging device characterized in that a control terminal of a switch element for operating a circuit is shared.

Further, an object of the present invention is to have a plurality of pixels arranged in a horizontal direction and a vertical direction, each pixel having a photoelectric conversion element, a reset switch for sweeping out electric charges accumulated in the photoelectric conversion element, A sample and hold circuit for sampling and holding the charge as a signal, a random reset circuit for driving a reset switch of a designated pixel, and a sample and hold circuit for sampling and holding a signal of a designated pixel in the sample and hold circuit A random sample circuit, and a solid-state imaging device including a random access circuit for reading a signal of a sample and hold circuit of a specified pixel, wherein the random reset circuit, the random sample circuit and the random access circuit, Specify the circuit or vertical address to specify. It was common one of the circuit to be achieved by the solid-state imaging device according to claim.

It is another object of the present invention to have a plurality of pixels arranged in a horizontal direction and a vertical direction, each pixel having a photoelectric conversion element, and a reset switch for sweeping out electric charges accumulated in the photoelectric conversion element. A sample and hold circuit for sampling and holding the charge as a signal, a random reset circuit for driving a reset switch of a specified pixel, and a sample and hold circuit for sampling and holding a signal of a specified pixel. And a random access circuit for reading a signal of a sample and hold circuit of a designated pixel, the random reset circuit, the random sample circuit and the random access circuit, the horizontal address Specify the circuit and vertical address to specify While each common circuitry for the random reset circuit of the designated pixel is accomplished by the solid-state imaging device, characterized in that a switching element for operating the random sample circuit and a random access circuit.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. [First Embodiment] FIG. 1 is a circuit diagram showing a first embodiment of the solid-state imaging device of the present invention. In FIG. 1, the same portions as those of the conventional solid-state imaging device shown in FIG. 25 are denoted by the same reference numerals, and detailed description thereof will be omitted. In FIG. 1, reference numeral 28 denotes an H-direction access reset address decoder in which a circuit for designating an H-direction address of the random access circuit and the random reset circuit is shared, and 29 denotes a V-direction address of the random access circuit and the random reset circuit. This is a V-direction access reset address decoder in which a circuit for designating is shared. The other configuration is the same as the conventional one shown in FIG.

FIG. 2 is a diagram showing a specific circuit configuration of the pixel 2 of the solid-state imaging device. In this embodiment, the gates of the H-direction access pass transistor T8 and the H-direction reset pass transistor T10 are all connected to the H-direction address line 6 of the H-direction access reset decoder 28. The gates of the V-direction access pass transistor T7 and the V-direction reset pass transistor T9 are all connected to the V-direction address line 10 of the V-direction access reset decoder 29. Thereby, in the pixel selected by the H-direction access reset address pulse φHa / r and the V-direction access reset address pulse φVa / r, the sampled and held image signal is read out and the pixel is simultaneously reset. Have been.

FIG. 3 is a diagram showing an arrangement of the pixels 2 of the solid-state imaging device. Here, a description will be given by taking three rows and three columns as an example. (11), (12), (13), ... (32), (3)
3) are pixels shown in a matrix. For example, in (13), 1 indicates a V direction address, and 3 indicates an H direction address.

FIG. 4 shows the operation states of the random access circuit (denoted by A), the random reset circuit (denoted by R), and the random sampling circuit (denoted by S) for each pixel corresponding to the passage of time, and FIG. FIG. 5 is a diagram illustrating a comparison result of a reference signal and an image signal of a corresponding pixel by a comparator. In the comparison results, 〇 is coincident and × is not coincident. Hereinafter, the operation of the solid-state imaging device according to the present embodiment will be described with reference to FIG. In FIG. 4, after the first exposure is performed under a certain exposure condition, the charges stored in the photodiodes D1 and the storage capacitors C1 of all the pixels are converted into a voltage by operating the random sampling circuit, and a predetermined sequence is performed. Is sampled and held. Thereafter, by operating the random access circuit, the image signals in which all the pixels are sampled and held are read out in a predetermined order, the pixels are simultaneously reset, and re-exposure is started. In this case, the comparison result of the comparator 18 in the first readout indicates that the pixel (12),
In (13) and (23), the result is x, and the pixel signal does not match the reference signal. Therefore, at this time, the addresses of these pixels are stored in the address memory 21. After an appropriate exposure time has elapsed, the signal charge of the pixel (12) is sampled and held. In this embodiment, the random access circuit and the random reset circuit operate simultaneously, but the random sample circuit operates independently. It is possible to operate. Therefore, simultaneously with the operation of the random access circuit and the random reset circuit of the pixel (31), the signal charge re-exposed by operating the random sample circuit of the pixel (12) based on the information of the address memory 21 is sampled and held. Pixel (1
For 3) and (23), re-exposure is performed in the same procedure. Then, as a second reading, image signals in which all pixels are sampled and held are read in a predetermined order.

As described above, in this embodiment, of the random reset circuit and the random access circuit, the circuit for designating the H-direction address and the circuit for designating the V-direction address are commonly used, so that the configuration of the solid-state imaging device is improved. It can be greatly simplified and the scale can be reduced. In addition, since the random sampling circuit operates independently, the dynamic range of the solid-state imaging device can be expanded as in the conventional case. [Second Embodiment] FIG. 5 shows the operation states of a random access circuit, a random reset circuit, and a random sampling circuit for each pixel in the second embodiment of the present invention, and the image signal of the pixel corresponding to the reference signal by the comparator 18. It is a figure showing the comparison result of. Here, it is assumed that the solid-state imaging device shown in the first embodiment is used. Further, in this embodiment, the random access circuit is operated, and the repetition time for reading out the signals of the sample and hold circuits of a plurality of pixels in a predetermined order is divided into two, and one of them operates the random access circuit and the random reset circuit. And the other is allocated to the time when the random sampling circuit operates. FIGS. 5A and 5B show a series of operations, and FIG. 5B is followed by FIG.

The first read operation is performed by operating the random access circuit as in the first embodiment, and the comparator 18 compares the read pixel signal with the reference signal. In this comparison result, pixels (12) and (13)
And (23) do not match the reference signal, and the addresses of these pixels are stored in the address memory 21. On the other hand, since the random reset circuit operates simultaneously with the random access circuit, re-exposure has already started. After the appropriate exposure time has elapsed, the random sampling circuit is operated. In the present embodiment, the time during which the random access circuit and the random reset circuit are operating and the time during which the random sampling circuit is operating are described. Being independent,
After the random access circuit and the random reset circuit of the pixel (31) operate, the random sample circuit of the pixel (12) is operated based on the information of the address memory 21,
The re-exposed signal charges are sampled and held. The pixels (13) and (23) are re-exposed in the same procedure. Then, as a second reading, image signals in which all pixels are sampled and held are read in a predetermined order.

Also in the present embodiment, the circuit for designating the H-direction address and the circuit for designating the V-direction address among the random reset circuit and the random access circuit are commonly used, so that the configuration of the solid-state imaging device can be simplified. In addition, the dynamic range can be expanded. Third Embodiment FIG. 6 is a diagram showing a third embodiment of the solid-state imaging device of the present invention. In FIG. 6, reference numeral 23 denotes an H-direction common address decoder in which a circuit for designating an H-direction address among a random access circuit, a random reset circuit, and a random sample circuit is shared, and 29 denotes V in the random access circuit and the random reset circuit. This is a V-direction access reset address decoder in which a circuit for designating a direction address is shared. Other configurations are the same as those of the first embodiment.

FIG. 7 is a diagram showing a configuration of the pixel 2 of the solid-state image sensor of FIG. In this example, the H-direction access pass transistor T8 and the H-direction reset pass transistor T1
The gates of the 0 and H direction sample pass transistors T12 are all connected to the H direction address line 6 of the H direction common decoder 23.
It is connected to the. The gates of the V-direction access pass transistor T7 and the V-direction reset pass transistor T9 are also all V-direction access reset decoders 29.
It is connected to a direction address line 10. Thereby, H
H-direction access pass transistors T8 of all pixels in one row in the V direction selected by the direction common address pulse φHc,
The H-direction reset pass transistor T10 and the H-direction sample pass transistor T12 are turned on. Also,
The pixel selected by the V-direction access reset address pulse φVa / r is configured to read the sampled and held image signal and reset the pixel simultaneously. Note that the arrangement of the pixels of the solid-state imaging device is three rows and three columns as shown in FIG.

FIG. 8 shows the operating states of the random access circuit (denoted by A), the random reset circuit (denoted by R), and the random sampling circuit (denoted by S) for each pixel corresponding to the passage of time, and the reference by the comparator 18. FIG. 9 is a diagram illustrating a comparison result between a signal and an image signal of a corresponding pixel. The operation of the solid-state imaging device according to the present embodiment will be described with reference to FIG. First, after the first exposure is performed under a certain exposure condition, the charges stored in the photodiodes D1 and the storage capacitors C1 of all the pixels are converted by operating the random sampling circuit,
The samples are held in a predetermined order. Next, an image signal in which all pixels are sampled and held by operating the random access circuit is read out in a predetermined order,
The pixels are reset at the same time, and re-exposure is started.
In this case, in the first reading, the comparison result of the comparator 18 is as shown in FIG.
Are not matched with the reference signal, the addresses of these pixels are stored in the address memory 21. After an appropriate exposure time has elapsed, the signal charge of the pixel (12) is sampled and held. In this embodiment, the H-direction address decoder of the pixel (12) is used in common since the H-direction address decoder is shared. Is selected for the pixel (2
2), (32)... When the random access circuits are operating. For example, assuming that the random access circuit of the pixel (32) is operating, at this time, the random sample circuit of the pixel (12) is operated by the V-direction decoder of the random sample circuit based on the information of the address memory 21 to re-execute. The exposed signal charges are sampled and held. Sampling and holding are performed for pixels (13) and (23) in the same manner. Then, as a second reading, an image signal in which all pixels are sampled and held is read in a predetermined order. In the present embodiment, the V-direction address decoder of the random access circuit and the random reset circuit is shared, and the H-direction address decoder is shared, so that the configuration of the solid-state imaging device can be simplified and the dynamic range is expanded. can do. [Fourth Embodiment] A fourth embodiment of the present invention will be described with reference to FIG. This embodiment is an example in which the solid-state imaging device of the third embodiment shown in FIG. 6 is used as a solid-state imaging device. In FIG. 5, first, the first reading is performed as in the third embodiment, and the comparator 18 compares the pixel signal with the reference signal. According to the comparison result of the comparator 18, the pixels (12),
It can be seen that (13) and (23) do not match the reference signal. On the other hand, the pixel has already been reset and re-exposure has started. After the random access circuit of the pixel (31) operates, the signal charges re-exposed by operating the random sample circuit of the pixel (12) are sampled and held. Sampling and holding are performed for pixels (13) and (23) in the same manner. Next, as a second reading, an image signal in which all pixels are sampled and held is read in a predetermined order. Here, in the third embodiment, the setting of the re-exposure time of a certain pixel, that is, the operation of the random reset circuit and the operation of the random sample circuit are restricted when the same H-direction address is designated, so that the exposure time is reduced. Although the setting is limited to the unit of the horizontal scanning period, in this embodiment, the time when the random access circuit and the random reset circuit are operating and the time when the random sampling circuit is operating are independent, By re-designating the H-direction address and the V-direction address, it becomes possible to set an exposure time in units of repetition time when reading out pixel signals in a predetermined order. [Fifth Embodiment] FIG. 9 is a diagram showing a fifth embodiment of the solid-state imaging device of the present invention. In FIG. 9, reference numeral 24 denotes a V-direction common address decoder in which a circuit for designating a V-direction address among a random access circuit, a random reset circuit, and a random sample circuit is shared, and 28 denotes H among the random access circuit and the random reset circuit. This is an H-direction access reset address decoder in which a circuit for designating a direction address is shared. FIG.
In the figure, the gates of the V-direction access pass transistor T7, V-direction reset pass transistor T9, and V-direction sample pass transistor T11 are all connected to the V-direction address line 10 of the V-direction common decoder 24. Have been. Further, the H-direction access pass transistor T8 and the H-direction reset pass transistor T
All 10 gates are connected to the H-direction address line 6 of the H-direction access reset decoder 28. Thus, the V-direction access pass transistors T7, V-direction reset pass transistors T9, and V of all the pixels in one row in the H direction selected by the V-direction common address pulse φVc.
The direction sample pass transistor T11 is turned on. Also, an H-direction access reset address pulse φH
The pixel selected by a / r is configured to read the sampled and held image signal and reset the pixel at the same time. The arrangement of the pixels of the solid-state imaging device is three rows and three columns as shown in FIG.

FIG. 11 shows the operation states of the random access circuit (denoted by A), the random reset circuit (denoted by R), and the random sampling circuit (denoted by S) for each pixel corresponding to the passage of time, and the reference by the comparator 18. FIG. 9 is a diagram illustrating a comparison result between a signal and an image signal of a corresponding pixel. The operation of this embodiment will be described with reference to FIG. First, after the first exposure is performed under a certain exposure condition, the charges stored in the photodiodes D1 and the storage capacitors C1 of all the pixels are converted into voltages by operating the random sampling circuit, and sample-and-hold is performed in a predetermined order. Is done. Next, the random access circuit is operated to read out the image signals in which all the pixels are sampled and held in a predetermined order, and the pixels are simultaneously reset and re-exposure is started. This is the first reading, and the comparison result of the comparator 18 indicates that the pixel (1
Since it is known that 1) and (21) do not match the reference signal, the addresses of these pixels are stored in the address memory 21. After an appropriate exposure time has elapsed, the signal charge of the pixel (11) is sampled and held. In this embodiment, since the V-direction address decoder is shared, the V-direction address of the pixel (11) is not changed. The selection is either now or after one vertical scan period. Here, the case where the V-direction address is currently selected is shown. When the random access circuit of the pixel (13) is operating, the pixel in the H-direction decoder of the random sampling circuit is determined based on the information in the address memory 21. The random sample circuit of (11) is operated, and the signal charges re-exposed are sampled and held. The sample hold is performed on the pixel (21) in the same procedure. Then, as a second reading, image signals in which all pixels are sampled and held are read in a predetermined order. Also in the present embodiment, the H-direction address decoder of the random access circuit and the random reset circuit is shared, and the V-direction address decoder is shared, so that the configuration of the solid-state imaging device can be simplified and the dynamic range is expanded. can do. Sixth Embodiment A sixth embodiment of the present invention will be described with reference to FIG. This embodiment is an example in which the solid-state imaging device of the fifth embodiment shown in FIG. 9 is used as a solid-state imaging device. First, the first reading is performed as in the fifth embodiment, and the comparator 18 compares the pixel signal with the reference signal. The comparison result of the comparator 18 indicates that the pixels (12), (13) and (23) do not match the reference signal. On the other hand, the pixel has already been reset and re-exposure has started.
After the random access circuit of the pixel (31) operates, the signal charges re-exposed by operating the random sample circuit of the pixel (12) are sampled and held. Sampling and holding are performed for pixels (13) and (23) in the same manner. Next, as a second reading, an image signal in which all pixels are sampled and held is read in a predetermined order. Here, in the fifth embodiment, the setting of the re-exposure time of a certain pixel, that is, the operation of the random reset circuit and the operation of the random sample circuit are restricted when the same V-direction address is specified. The setting is limited to within the current horizontal scanning period or within one horizontal scanning period for each vertical scanning period. In this embodiment, the time during which the random access circuit and the random reset circuit are operating and the random sampling circuit Since the operation times of the pixel signals are independent, it is possible to set the exposure time in the unit of repetition time when reading the pixel signals in a predetermined order by re-designating the H-direction address and the V-direction address. [Seventh Embodiment] FIG. 12 is a view showing a solid-state imaging device according to a seventh embodiment of the present invention. In FIG. 12, reference numeral 23 denotes an H-direction common address decoder in which a circuit for designating an H-direction address among a random access circuit, a random reset circuit, and a random sample circuit is shared. Among the circuits, a V-direction common address decoder in which a circuit for designating a V-direction address is shared, 27 is a sample control line connected to the gate of the sample control path transistor T17 of all pixels, and 30 is an access control path of all pixels An access reset control line connected to the gate of the transistor T13 and the gate of the reset control pass transistor T15 of all pixels.

FIG. 13 is a diagram showing the pixel 2 of the solid-state image sensor of FIG. Here, the H-direction address pass transistor T whose gate is connected to the H-direction address line 6
20 and the gate whose gate is connected to the V-direction address line 10
The direction address pass transistor T19 is connected in series, and the output terminal of the transistor T19 is connected to the gates of the access pass transistor T14, the reset pass transistor T16, and the sample pass transistor T18. As a result, the access pass transistor T14 of one pixel selected by the H-direction common address pulse φHc and the V-direction common address pulse φVc,
The reset pass transistor T16 and the sample pass transistor T18 turn on. Further, a random access circuit, a random reset circuit and a random sample circuit are respectively selected and operated by the access reset control pulse φCa / r and the sample control pulse φCs. The arrangement of the pixels of the solid-state imaging device is three rows and three columns as shown in FIG.

FIG. 14 shows the operation states of the random access circuit (denoted by A), the random reset circuit (denoted by R) and the random sampling circuit (denoted by S) for each pixel corresponding to the passage of time, and the selected access reset. Control pulse φCa / r and sample control pulse φC
5A and 5B are diagrams illustrating a comparison result between the reference signal and an image signal of a corresponding pixel by the comparator. Here, the random access circuit is operated, and the repetition time for reading out the signals of the sample and hold circuits of a plurality of pixels in a predetermined order is divided into two, and one of them is the time during which the random access circuit and the random reset circuit operate. And the other is allocated to the time when the random sample circuit operates. 14 shows a series of operations, and FIG. 14 (a) is followed by FIG. 14 (b). FIG. 1 shows the operation of this embodiment.
4 will be described. First, after the first exposure is performed under a certain exposure condition, the charges stored in the photodiodes D1 and the storage capacitors C1 of all the pixels are converted into voltages by operating the random sampling circuit, and sample-and-hold is performed in a predetermined order. Is done. Next, the random access circuit is operated to read out the image signals in which all the pixels are sampled and held in a predetermined order, and the pixels are simultaneously reset and re-exposure is started. This is the first reading, and the comparison result of the comparator 18 indicates that the pixels (12) and (1)
Since it is found that 3) and (23) do not match the reference signal, the addresses of these pixels are stored in the address memory 21. After an appropriate exposure time has elapsed, the signal charge of the pixel (12) is sampled and held. In this embodiment, the time during which the random access circuit and the random reset circuit are operating and the time when the random sampling circuit is operating are described. After the random access circuit and the random reset circuit of the pixel (31) operate, first, the H-direction common address decoder 23 and the V-direction common address decoder 24, based on the information in the address memory 21, operate independently. Pixel (12) is selected. Next, the random sample circuit is operated by the sample control pulse φCs, and the signal charges re-exposed are sampled and held. Sampling and holding are performed for pixels (13) and (23) in the same manner. Then, as a second reading, an image signal in which all pixels are sampled and held is read in a predetermined order. In this embodiment, H
The common direction address decoder and the V-direction address decoder and the common access reset control line for the random access circuit and the random reset circuit can be used to simplify the configuration of the solid-state imaging device and increase the dynamic range. Can be expanded. [Eighth Embodiment] FIG. 15 is a view showing an eighth embodiment of the solid-state imaging device of the present invention. In FIG. 15, reference numeral 23 denotes an H-direction common address decoder in which a circuit for designating an H-direction address among a random access circuit, a random reset circuit, and a random sampling circuit is shared. FIG.
6 is a diagram showing a pixel 2 of the solid-state imaging device of FIG.
The gates of the H-direction access pass transistor T8, the H-direction reset pass transistor T10, and the H-direction sample pass transistor T12 are all H-direction common decoders 23.
To the H-direction address line 6. This allows
The H-direction access pass transistors T8, H-direction reset pass transistors T10, and H-direction sample pass transistors T12 of all the pixels in one row in the V direction selected by the H-direction common address pulse φHc are turned on.
The arrangement of the pixels of the solid-state image sensor is three rows and three pixels as shown in FIG.
It shall be a column. FIG. 17 shows the operation states of the random access circuit (indicated by A), the random reset circuit (indicated by R), and the random sampling circuit (indicated by S) for each pixel corresponding to the passage of time and the reference signal by the comparator 18. FIG. 7 is a diagram illustrating a comparison result with an image signal of a corresponding pixel. The operation of this embodiment will be described with reference to FIG. First, after the first exposure is performed under a certain exposure condition, the charges stored in the photodiodes D1 and the storage capacitors C1 of all the pixels are converted into voltages by operating the random sampling circuit, and sample-and-hold is performed in a predetermined order. Is done. Next, the random access circuit is operated to read out the image signals in which all the pixels are sampled and held in a predetermined order. This is the first reading, and the comparison result of the comparator 18 indicates that the pixel (1
Since 2), (13) and (23) do not match the reference signal, the addresses of these pixels are stored in the address memory 21. In this embodiment, since the address decoder in the H direction is shared, the pixel (1
The H direction address of 2) is selected because the pixel (22)
It is when the random access circuit is operating. At this time, the random reset circuit of the pixel (12) is operated by the V-direction decoder of the random reset circuit based on the information in the address memory 21, and re-exposure is started. Pixel (1
For 3) and (23), re-exposure is performed in the same procedure. After an appropriate exposure time has elapsed, the signal charges of the pixel (12) are sampled and held. In this embodiment, the random access of the pixel (32) whose H-direction address of the pixel (12) is selected is also performed. While the circuit is operating, the random sample circuit of the pixel (12) is operated by the V-direction decoder of the random sample circuit based on the information in the address memory 21, and the re-exposed signal charges are sampled and held. Sampling and holding are performed for pixels (13) and (23) in the same manner. Then, as a second reading, an image signal in which all the pixels are sampled and held is read in a predetermined order. In this embodiment, the configuration of the solid-state imaging device can be simplified by sharing the address decoder in the H direction, and the dynamic range can be expanded. Ninth Embodiment A ninth embodiment of the present invention will be described with reference to FIG. FIG. 18 shows a random access circuit (denoted by A), a random reset circuit (denoted by R), and a random sampling circuit (denoted by S) for each pixel corresponding to the passage of time.
FIG. 5 is a diagram showing a comparison result between the operation state of FIG. 5 and a reference signal and an image signal of a corresponding pixel by a comparator 18. Here, the solid-state imaging device of the eighth embodiment is used.
In this embodiment, the random access circuit is operated,
The repetition time when reading the signals of the sample and hold circuits of a plurality of pixels in a predetermined order is divided into three, and the divided times are respectively the time during which the random access circuit operates, the time during which the random sample circuit operates, and the random time. It is assigned to the time when the reset circuit operates.
Further, FIG. 18 shows a series of operations, and FIG. 18 (b) is continued after FIG. 18 (a). In FIG. 18, first reading is performed, and the comparator 18 compares the pixel signal with the reference signal. The comparison result of the comparator 18 indicates that the pixels (12), (13), and (23) do not match the reference signal. Therefore, after the random access circuit of the pixel (12) operates, the random number of the pixel (12) is changed. By operating the reset circuit, re-exposure is started. The pixels (13) and (23) are re-exposed in the same procedure. Then, after the random access circuit of the pixel (31) operates, the random sampling circuit of the pixel (12) operates,
The re-exposed signal charges are sampled and held. Sampling and holding are performed for pixels (13) and (23) in the same manner. Next, as a second reading, an image signal in which all pixels are sampled and held is read in a predetermined order. Here, in the eighth embodiment, the setting of the re-exposure time of a certain pixel, that is, the operation of the random reset circuit and the operation of the random sample circuit are restricted when the same H-direction address is designated, so that the exposure time is reduced. Although the setting is limited to the unit of the horizontal scanning period, in this embodiment, the time during which the random access circuit operates, the time during which the random sampling circuit operates, and the time during which the random reset circuit operates are independent. Therefore, by re-designating the H-direction address and the V-direction address, it becomes possible to set the exposure time in units of repetition time when reading out pixel signals in a predetermined order. [Tenth Embodiment] FIG. 19 shows a first embodiment of the solid-state imaging device according to the present invention.
It is the figure which showed Example 0. In FIG. 19, reference numeral 24 denotes a V-direction common address decoder in which a circuit for designating a V-direction address among the random access circuit, the random reset circuit, and the random sampling circuit is shared.
FIG. 20 is a diagram showing a pixel 2 of the solid-state imaging device of FIG.
The gates of the V-direction access pass transistor T7, the V-direction reset pass transistor T9, and the V-direction sample pass transistor T11 are all connected to the V-direction address line 10 of the V-direction common decoder 24. This allows
The V-direction access pass transistors T7, V-direction reset pass transistors T9, and V-direction sample pass transistors T11 of all the pixels in one row in the H direction selected by the V-direction common address pulse φVc are turned on. The arrangement of the pixels of the solid-state imaging device is three rows and three columns as shown in FIG. FIG. 21 shows the operation states of the random access circuit (indicated by A), the random reset circuit (indicated by R), and the random sampling circuit (indicated by S) for each pixel corresponding to the passage of time, and the correspondence with the reference signal by the comparator 18. FIG. 7 is a diagram illustrating a comparison result with an image signal of a corresponding pixel. The operation of this embodiment will be described with reference to FIG. First, after the first exposure is performed under a certain exposure condition, the charges stored in the photodiodes D1 and the storage capacitors C1 of all the pixels are converted into voltages by operating the random sampling circuit, and sample-and-hold is performed in a predetermined order. Is done. Next, the random access circuit is operated to read out the image signals in which all the pixels are sampled and held in a predetermined order. This is the first reading, and the comparison result of the comparator 18 indicates that the pixel (1
Since it is known that 1) and (21) do not match the reference signal, the addresses of these pixels are stored in the address memory 21. In this embodiment, since the V-direction address decoder is shared, the V-direction address of the pixel (11) is selected at the present time or after one vertical scanning period.

FIG. 21 shows a case where the V-direction address is currently selected, which is when the random access circuit of the pixel (12) is operating. At this time, the random reset circuit of the pixel (11) is operated by the H-direction decoder of the random reset circuit based on the information in the address memory 21, and re-exposure is started. Re-exposure of the pixel (21) is started in the same procedure. After an appropriate exposure time has elapsed, the signal charge of the pixel (11) is sampled and held.
When the random access circuit of the pixel (13) whose V direction address is selected is operating, the random sample circuit of the pixel (11) is operated by the H direction decoder of the random sample circuit based on the information of the address memory 21. The re-exposed signal charges are sampled and held. The sample hold is performed on the pixel (21) in the same procedure. Then, as the second reading, the image signals sampled and held by all the pixels are read in a predetermined order. In this embodiment, since the address decoder in the V direction is shared, the configuration of the solid-state imaging device can be simplified and the dynamic range can be expanded. [Eleventh Embodiment] An eleventh embodiment of the present invention will be described with reference to FIG. In this embodiment, a solid-state imaging device shown in FIG.
This is an example when the solid-state imaging device of the tenth embodiment shown in FIG. In FIG. 18, first reading is performed, and the comparator 18 compares the pixel signal with the reference signal. According to the comparison result of the comparator 18, the pixels (12), (1)
Since it is found that 3) and (23) do not match the reference signal, after the random access circuit of the pixel (12) is operated, the random reset circuit of the pixel (12) is operated to start re-exposure. The pixels (13) and (23) are re-exposed in the same procedure. Then, the pixel (3
After the random access circuit of 1) operates, the pixel (1)
The random sampling circuit of 2) is operated, and the signal charges re-exposed are sampled and held. Sampling and holding are performed for pixels (13) and (23) in the same manner. Next, as a second reading, an image signal in which all pixels are sampled and held is read in a predetermined order. Here, in the tenth embodiment, the setting of the re-exposure time of a certain pixel, that is, the operation of the random reset circuit and the operation of the random sample circuit are restricted when the same V-direction address is specified. The setting is limited to within the current horizontal scanning period or within one horizontal scanning period for each vertical scanning period. In the present embodiment, the random sampling circuit operates while the random access circuit operates. Since the time and the operation time of the random reset circuit are independent, setting the H-direction address and the V-direction address again sets the exposure time in the unit of repetition time when reading out the pixel signals in a predetermined order. Becomes possible. [Twelfth Embodiment] FIG. 22 shows a first embodiment of the solid-state imaging device of the present invention.
It is a figure showing two examples. In FIG. 22, reference numeral 23 denotes an H-direction common address decoder in which a circuit for designating an H-direction address among a random access circuit, a random reset circuit, and a random sample circuit is shared, and 24, a random access circuit, a random reset circuit, and a random sample circuit A V-direction common address decoder 25 which shares a circuit for designating a V-direction address among the circuits;
Is the access control pass transistor T1 for all pixels
Access control line connected to gate 3
Is the reset control pass transistor T1 for all pixels
Reset control line 27 connected to the gate
Is the reset control pass transistor T1 for all pixels
7 is a sample control line connected to the 7th gate.

FIG. 23 is a diagram showing a pixel 2 of the solid-state imaging device of the twelfth embodiment. The H-direction address pass transistor T20 whose gate is connected to the H-direction address line 6 and the gate is connected to the V-direction address line 10. The connected V-direction address pass transistor T19 is connected in series, and the output of the transistor T19 is connected to an access pass transistor T14, a reset pass transistor T16, and a sample pass transistor T1 whose gates are commonly connected.
8 gates. As a result, the H-direction common address pulse φHc and the V-direction common address pulse φ
The access pass transistor T14, reset pass transistor T16, and sample pass transistor T18 of one pixel selected by Vc are turned on. The random access circuit, the random reset circuit, and the random sample circuit are selected and operated by the access control pulse φCa, the reset control pulse φCr, and the sample control pulse φCs, respectively. The arrangement of the pixels of the solid-state imaging device is shown in FIG.
As shown in FIG.

FIG. 24 shows the operating states of the random access circuit (denoted by A), the random reset circuit (denoted by R) and the random sampling circuit (denoted by S) for each pixel corresponding to the passage of time, and the selected access control. FIG. 4 is a diagram illustrating a comparison result between a pulse φCa, a reset control pulse φCr, a sample control pulse φCs, and a reference signal by a comparator 18 and an image signal of a corresponding pixel. Here, the random access circuit is operated, and the repetition time when reading out the signals of the sample and hold circuits of a plurality of pixels in a predetermined order is divided into three, and the divided times operate the random access circuit respectively. The time is assigned to the time when the random sampling circuit operates and the time when the random reset circuit operates. FIG. 24 shows a series of operations of the solid-state imaging device. FIG. 24A is followed by FIG.

The operation of this embodiment will be described with reference to FIG. First, after the first exposure under certain exposure conditions,
By operating the random sampling circuit, the charges stored in the photodiodes D1 and the storage capacitors C1 of all the pixels are converted into voltages and sampled and held in a predetermined order. Next, the random access circuit is operated to read out the image signals in which all the pixels are sampled and held in a predetermined order. This is the first reading, and since the comparison result of the comparator 18 indicates that the pixels (12), (13) and (23) do not match the reference signal, the addresses of these pixels are stored in the address memory 21. . In the present embodiment, the time during which the random access circuit operates, the time during which the random sampling circuit operates, and the time during which the random reset circuit operates are independent, so the random access circuit of the pixel (12) is independent. Then, after the random reset circuit operates, the pixel (12) is selected by the H-direction common address decoder 23 and the V-direction common address decoder 24 based on the information in the address memory 21. Next, the random reset circuit is operated by the reset control pulse φCr, and re-exposure is started. The pixels (13) and (23) are re-exposed in the same procedure. After an appropriate exposure time has elapsed, the signal charge of the pixel (12) is sampled and held. In the present embodiment, after the random access circuit of the pixel (31) operates, the signal charge of the pixel (31) is operated based on the information in the address memory 21. The pixel (12) is selected by the H-direction common address decoder 23 and the V-direction common address decoder 24. Thereafter, the random sample circuit is operated by the sample control pulse φCs, and the signal charges re-exposed are sampled and held. Sampling and holding are performed for pixels (13) and (23) in the same manner. Then, as the second reading, the image signals sampled and held by all the pixels are read in a predetermined order. Also in this embodiment, since the H-direction address decoder and the V-direction address decoder are commonly used, the configuration of the solid-state imaging device can be simplified and the dynamic range can be expanded.

[0031]

As described above, according to the present invention, the dynamic range can be expanded by commonly using the H-direction decoder and the V-direction decoder for operating the random reset circuit, the random sampling circuit and the random access circuit, respectively. At the same time, it is possible to reduce the circuit scale of the solid-state imaging device, and it is possible to reduce the size and cost of the device.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a solid-state imaging device according to the present invention.

FIG. 2 is a circuit diagram showing a configuration of a pixel in the embodiment of FIG.

FIG. 3 is a diagram illustrating an arrangement of pixels of a solid-state imaging device.

FIG. 4 is a diagram illustrating an operation of the solid-state imaging device according to the embodiment of FIG. 1;

FIG. 5 is a diagram showing a second embodiment and a fourth embodiment of the present invention.

FIG. 6 is a circuit diagram illustrating a solid-state imaging device according to a third embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration of a pixel in the embodiment of FIG.

FIG. 8 is a diagram illustrating an operation of the solid-state imaging device according to the embodiment of FIG. 6;

FIG. 9 is a circuit diagram showing a solid-state imaging device according to a fifth embodiment of the present invention.

FIG. 10 is a circuit diagram showing a configuration of a pixel in the embodiment of FIG. 9;

FIG. 11 is a diagram illustrating the operation of the solid-state imaging device according to the embodiment of FIG. 9;

FIG. 12 is a circuit diagram showing a solid-state imaging device according to a seventh embodiment of the present invention.

FIG. 13 is a circuit diagram showing a configuration of a pixel in the embodiment of FIG.

FIG. 14 is a diagram illustrating an operation of the solid-state imaging device according to the embodiment of FIG. 12;

FIG. 15 is a circuit diagram showing a solid-state imaging device according to an eighth embodiment of the present invention.

FIG. 16 is a circuit diagram showing a configuration of a pixel in the embodiment of FIG.

FIG. 17 is a diagram illustrating an operation of the solid-state imaging device according to the embodiment of FIG. 15;

FIG. 18 is a view showing a ninth embodiment and an eleventh embodiment of the present invention.

FIG. 19 is a circuit diagram showing a solid-state imaging device according to a tenth embodiment of the present invention.

20 is a circuit diagram showing a configuration of a pixel in the embodiment of FIG.

FIG. 21 is a diagram illustrating the operation of the solid-state imaging device according to the embodiment of FIG. 19;

FIG. 22 is a circuit diagram showing a twelfth embodiment of the solid-state imaging device according to the present invention.

FIG. 23 is a circuit diagram showing a configuration of a pixel in the embodiment of FIG.

FIG. 24 is a diagram illustrating an operation of the solid-state imaging device according to the embodiment of FIG. 22;

FIG. 25 is a circuit diagram showing a conventional solid-state imaging device.

26 is a circuit diagram illustrating a configuration of a pixel of the solid-state imaging device in FIG. 25.

FIG. 27 is a block diagram illustrating a configuration example of a solid-state imaging device using a solid-state imaging device.

[Explanation of symbols]

 Reference Signs List 1 imaging area 2 pixel 3-5 H direction decoder 7-9 V direction decoder 6 H direction address line 10 V direction address line 12 output circuit 23 H direction common address decoder 24 V direction common address decoder 28 H direction access reset address decoder 29 V-direction access reset address decoder D1 photodiode C1 storage capacitance

Claims (6)

(57) [Claims] An image display device includes a plurality of pixels arranged in a horizontal direction and a vertical direction. Each pixel has a photoelectric conversion element, a reset switch for sweeping out charges accumulated in the photoelectric conversion element, and the charge as a signal. With a sample and hold circuit for sample and hold, a random reset circuit for driving a reset switch of a specified pixel, and a random sample circuit for sample and hold a signal of a specified pixel in the sample and hold circuit A random access circuit for reading out a signal of a sample-and-hold circuit of a specified pixel, a circuit for specifying a horizontal address and a vertical address of the random reset circuit and the random access circuit. That the circuits for specifying A solid-state imaging device characterized by the above-mentioned. 2. The solid-state imaging device according to claim 1, wherein a circuit for designating a horizontal address of the random sampling circuit is shared. 3. The solid-state imaging device according to claim 1, wherein a circuit for designating a vertical address of said random sampling circuit is shared. 4. A plurality of pixels arranged in a horizontal direction and a vertical direction. Each pixel has a photoelectric conversion element, a reset switch for sweeping out charges accumulated in the photoelectric conversion element, and the charge as a signal. With a sample and hold circuit for sample and hold, a random reset circuit for driving a reset switch of a specified pixel, and a random sample circuit for sample and hold a signal of a specified pixel in the sample and hold circuit A random access circuit for reading out a signal of a sample and hold circuit of a designated pixel, a circuit for designating a horizontal address among the random reset circuit, the random sample circuit and the random access circuit And a circuit for specifying the vertical address A switch element for operating the random reset circuit, the random sample circuit, and the random access circuit of the designated pixel is provided, respectively, and the random reset circuit and the random access circuit among the switch elements are operated. A solid-state image sensor, wherein a control terminal of a switch element for the switch is shared. 5. A plurality of pixels arranged in a horizontal direction and a vertical direction. Each pixel has a photoelectric conversion element, a reset switch for sweeping out electric charges accumulated in the photoelectric conversion element, and the electric charges as signals. With a sample and hold circuit for sample and hold, a random reset circuit for driving a reset switch of a specified pixel, and a random sample circuit for sample and hold a signal of a specified pixel in the sample and hold circuit A random access circuit for reading out a signal of a sample and hold circuit of a designated pixel, a circuit for designating a horizontal address among the random reset circuit, the random sample circuit and the random access circuit Or a circuit to specify the vertical address A solid-state imaging device characterized in that at least one of them is shared. 6. A plurality of pixels arranged in a horizontal direction and a vertical direction. Each pixel has a photoelectric conversion element, a reset switch for sweeping out charges accumulated in the photoelectric conversion element, and the charge as a signal. With a sample and hold circuit for sample and hold, a random reset circuit for driving a reset switch of a specified pixel, and a random sample circuit for sample and hold a signal of a specified pixel in the sample and hold circuit A random access circuit for reading out a signal of a sample and hold circuit of a designated pixel, a circuit for designating a horizontal address among the random reset circuit, the random sample circuit and the random access circuit And a circuit for specifying the vertical address A solid-state imaging device having a common element and a switch element for operating a random reset circuit, a random sample circuit, and a random access circuit of a designated pixel.