JP3036449B2 - Memory diagnostic device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory diagnostic device, and more particularly to a memory diagnostic device divided into a plurality of banks.

[0002]

2. Description of the Related Art Various techniques for diagnosing memories have been proposed. The techniques disclosed in Japanese Patent Application Laid-Open Nos. 61-217848 and 2-133844 will be described.

In the former publication, two systems of a bus control circuit, a comparison / matching circuit and a read / write circuit are used in a memory verify circuit in order to compare and match at a high speed whether or not data written in a memory has been written without error. The configuration includes a write switching circuit. At the time of verification, first, the mode of the read / write switching circuit is set to the read state, the direction of the data bus is reversed, and then the data in the memory is read and compared with the data in the comparison / collation circuit. When the memory is cleared by the above circuit configuration, data "0" or "1" is sequentially written to a predetermined address sequentially by DMA (direct memory access), and then the above-described processing is performed.

In the latter JP-A-2-133844, a write data latch circuit for holding write data transferred on a data bus when writing data to a memory, and a write data latch circuit for reading data from the memory. A read data latch circuit for holding read data transferred on the data bus, and a compare circuit for comparing the output of the write data latch circuit with the output of the read latch circuit. Whether it was written without
A write data circuit and a read data latch circuit on a data bus latch data in a write cycle and a read cycle by DMA transfer, respectively, and compare the latched data with a compare circuit to diagnose a memory.

[0005]

In such a conventional memory write data diagnosis method, when diagnosing write data to a memory, the transfer performance is lowered by waiting for a memory access request from another device. Problem.

The reason for this is that when diagnosing data to be written to the memory, the read cycle for diagnosing the memory and access to the memory from other devices are arbitrated by the DMA controller. When the read request is permitted, a memory access request from another device is waited, and the transfer performance is reduced.

When the diagnosis of write data is performed not in the diagnostic cycle but in the normal read cycle to the same address, the data bus used for diagnosis and the data bus used for writing and reading are the same data bus. Is used, diagnosis of write data is performed after execution of a read cycle. If an error occurs in the read data, it is clear that the error is caused by mismatch of the write data, but there is a disadvantage that runaway of the system cannot be prevented in advance.

An object of the present invention is to prevent a system runaway caused by a write data error in a memory without deteriorating the transfer performance from another device to the memory even when performing a write data diagnosis of the memory. It is possible to provide a memory diagnostic device capable of performing the above.

[0009]

According to the present invention, there is provided an apparatus for diagnosing a memory divided into a plurality of banks, wherein when there is a write access to the memory, write data and access information as access information thereof are provided. A storage unit for storing an address, and in response to a write access to the memory, read out access information of a bank other than the bank to be accessed from the storage unit and execute a read for diagnosis to the bank. A memory diagnostic device is provided which includes diagnostic means for comparing read data with write data of the access information, and diagnoses the bank in accordance with a result of the comparison.

The diagnostic means determines whether or not access information other than the bank to be accessed is stored in the storage means in response to a write access to the memory. Affirmative, means for executing reading of the bank according to the access address of the access information relating to the bank, and comparing means for comparing read data obtained by the reading with write data of the access information, Further, the present invention is characterized in that an error signal is generated when the comparing means indicates a mismatch.

The operation of the present invention will be described. In the present invention, when there is a write access to a memory, the access information is temporarily stored in a buffer, and during access to a certain bank, access information of a bank other than the bank is stored in the buffer. Only when the access is performed, reading is performed to a bank other than the bank currently being accessed according to the access information, and the memory diagnosis of the bank is performed.

More specifically, when the DMA controller recognizes the memory access, the DMA controller notifies the diagnosis controller of the access information. Upon receiving the access information, the diagnostic control unit outputs a control signal to the bus switching unit to switch the bus connection. When access to the memory is in a write cycle, write data is always held in a write data buffer. When an access to a bank other than the held bank is executed, the bus switching unit of the bank holding the data is controlled to execute a data read cycle and input to the data comparison control unit. The read data is compared with the data held in the write data buffer, and memory write data diagnosis is performed. If the diagnosis result is an error, the error information is stored in the register.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In FIG. 1, when a DMA request signal 10 from each device (not shown) is input, a DMA controller unit 2 arbitrates a DAM request, and determines which bank of each of the memories 4a to 4c according to an address from an address bus 11. , And outputs an access information notification signal 12.

The bus switching units 5a, 5b, 5c are provided corresponding to the memories 4a, 4b, 4c, respectively.
The switching connection between the memory bus 14a for the A controller unit 2 and the memory buses 14b to 14d for the memories 4a to 4c, and the switching connection between the memory buses 14b to 14d and the bus 15 for memory diagnosis. .

The data diagnosis section 1 performs diagnosis of each of the memories 4a to 4c, and has a diagnosis control section 3, a data comparison control section 7, and an error register 8.

Upon receiving the access information notification signal 12 from the DMA controller 2, the diagnosis controller 3 temporarily stores the write data and the access address as the access information on the memory bus 14a in the write data buffer 6. At the same time, it is searched whether access information of a bank other than the one currently being accessed is stored in the buffer 6, and if stored, the access information of the bank is read out and the memory switching signal 13 is generated according to the access address. Then, a corresponding one of the bus switching units 5a to 5c is instructed to connect one of the memory buses (14b to 14d) to the memory diagnostic bus 15.

In this state, the diagnosis control unit 3 executes reading (according to the diagnosis control signal 18) in accordance with the access address stored in the buffer 6 for memory diagnosis, and reads the read data (memory diagnosis bus 15). ) And the write data (diagnosis bus 1) stored in the buffer 6.
6) is compared by the data comparison control unit 7.

When the comparison result indicates a mismatch, the data comparison control section 7 generates an error signal 17 and stores it in the error register 8.

FIG. 2 is a flowchart showing the operation of the data diagnostic unit 1 in the block shown in FIG. Referring to FIG.
Access information notification signal 12 from DMA controller 2
Is supplied (step S1), the bus switching units 5a to 5c are controlled in accordance with the access address of the access information on the memory bus 14a, and the connection between the memory bus 14a and one of the memory buses 14b to 14d is controlled (step S1). S2). Thereby, a memory access is executed.

At the same time, write data and access address as access information are stored in the buffer 6 (step S3). Then, it is determined whether or not write data to a bank other than the bank being accessed has already been stored in the buffer 6 (step S4). If not, the process returns to the first step S1.

If stored, the bus switching unit (5) connects the memory bus (one of 14b to 14d) of the bank corresponding to the write data to the memory diagnostic bus 15.
a to 5c) (step S5).

Thereafter, a memory access is performed by an access address corresponding to the write data by the diagnostic control signal 18 to read data (step S).
6). The read data and the write data in the buffer 6 are compared by the data comparison control unit 7 (Step S).
7).

If the comparison results in a match, the write data and access address are erased from the buffer 6 and
It returns to step S1 (step S9). If they do not match, it is regarded as an error and an error signal 17 is output and stored in the error register 8 (step S10).

The operation will be described below using a specific example.
For example, a case will be described in which diagnosis of write data to the memory 4a is performed during access to the memory 4b.

The DMA request 10 is sent to the DMA controller 2.
When a memory access request and an address are input via the address bus 11 and the DMA controller 2, respectively.
Recognizes which bank the access request is for.

The DMA controller 2 executes a write cycle for the memory 4a and outputs an access information notification signal 12 to notify the diagnosis controller 3 of access information. In response to the access information notification signal 12, the diagnosis control unit 3 outputs a memory switching signal 13 to control the bus switching unit 5a, connect the memory buses 4a and 14b, and connect the memory data bus 6 to the write data buffer 6. 4
The write data and the access address are stored via a.

After the write cycle of memory 4a is completed, a read cycle for memory 4b is performed.
The DMA controller 2 outputs an access information notification signal 12 to the diagnosis controller 3. The diagnosis control unit 3 recognizes the access to the memory 4b and outputs a memory switching signal 13,
The connection between the memory buses 14a and 14c is controlled.

At the same time, the buffer 6 is searched to detect that the data written to the memory 4a is stored in the buffer 6, and the switching signal 13 is used for diagnosing the memory 4a by using the access to the memory 4b as a trigger. To control the bus switching unit 5a to connect the memory bus 4b to the memory diagnostic bus 15.

Further, a diagnostic control signal 18 is also output to perform a read access to the memory 4a corresponding to the write address held in the buffer 6, thereby executing a data read from the memory 4a. Then, the write data stored in the buffer 6 and the read data are compared by the comparison control unit 7, and diagnosis is performed.

[0031]

As described above, according to the present invention, by dividing a memory into a plurality of banks and controlling memory access on a bank basis, data can be read from another bank during memory access. Therefore, the memory write data can be diagnosed without degrading the performance of memory transfer from another device, and the system can be prevented from running out of control due to a data write error in advance.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a flowchart illustrating an operation of a data diagnostic unit in FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Data diagnostic part 2 DMA controller part 3 Diagnosis control part 4a-4c memory 5a-5c Bus switching part 6 Buffer for write data 7 Data comparison control part 8 Error register

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 12/16 330

Claims (3)

(57) [Claims] 1. A diagnostic device for a memory divided into a plurality of banks, wherein when there is a write access to the memory, storage means for storing write data and access address as access information thereof, and the memory In response to a write access to the bank, access information of a bank other than the bank to be accessed is read from the storage means, and a read for diagnosis is performed on the bank, and the read data and the write of the access information are written. Diagnostic means for comparing the data with data, and diagnosing the bank in accordance with the result of the comparison. 2. The diagnostic device according to claim 1, further comprising: a determining unit configured to determine, in response to a write access to the memory, whether the storage unit stores access information other than the bank to be accessed. When the result is affirmative, there is provided means for executing reading of the bank in accordance with the access address of the access information relating to the bank, and comparing means for comparing read data obtained by the reading with write data of the access information. Item 2. The memory diagnostic device according to Item 1. 3. An error signal is generated when the comparing means indicates a mismatch.
A memory diagnostic device according to claim 1.