JP2946504B2 - Time axis multiplex operation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order. A. Industrial application fields B. Summary of the invention C. Prior art D. Problems to be solved by the invention E. Means for solving the problems F. Action G. Embodiment G-1. G-2. Equivalent circuit and basic operation of the embodiment (FIG. 2, FIG. 3)
G-3. Specific configuration and operation of the embodiment (FIGS. 4 and 5)
FIG. G-4. Other Embodiments H. Effects of the Invention A. Industrial Application Field of the Invention The present invention relates to a time axis multiplexing operation circuit, and more particularly, to a time axis for executing so-called cumulative addition by time axis multiplexing. It relates to a multiplex operation circuit. B. Summary of the Invention The present invention relates to a time axis multiplexing operation circuit for performing time axis multiplexing operation processing on input data and outputting the input data register, wherein at least two registers to which input data is supplied are connected in series. Circuit, and a plurality of output data register circuits in which at least two registers to which operation output data from the arithmetic unit are supplied are directly connected. The time-division multiplexed output data is obtained from the register circuit, and the output data is sent to an arithmetic unit via a multiplexer, and the arithmetic unit performs time-division multiplexing arithmetic processing, so that accumulation and the like can be performed with a simple configuration. The operation can be performed at a relatively high speed. C. Prior Art Conventionally, so-called pipeline processing has been known as one method for speeding up arithmetic processing. In the pipeline processing, the processing operation is divided into several elements, and the operation of each element is performed in a continuous and parallel manner in a flow operation. A so-called pipeline adder that applies this to the most basic operation, an addition operation, equivalently operates as an adder having a predetermined number of delay stages. An addition output of the data supplied to each input terminal of the pipeline adder is taken out from the output terminal after the predetermined delay time has elapsed. Using such a pipeline adder,
For example, when an accumulation circuit is to be formed, a normal accumulation operation is not performed simply by feeding back the addition output from the output terminal to one of the addition input terminals. In view of this, the applicant of the present application has previously proposed a cumulative addition circuit (accumulation circuit) as shown in FIG. 6 in Japanese Patent Application No. 62-65270. FIG. 6 shows an example of an accumulator circuit using a pipeline adder (with a delay of k samples) having a general number of delay stages for k clocks (k is an integer). N in the figure
Is an integer satisfying 2 ^n-1 <k <2 ⁿ , and 2 ⁿ ≡N. L is the number of samples for obtaining a moving average. In FIG. 6, the symbols z ⁻¹ , z ⁻² ... Z ^{−N / 2} shown in the registers R ₀ , R ₁ ... R _n−1 are 1 (= 2 ⁰ ) sample delay and 2 ( = 2 ¹ ) Sample delay ... N / 2 (= 2 ^n-1 )
It represents the delay of a power of two sample, such as the sample delay. These n registers R _0, R ₁ ... by the k sample delay pipeline adder _{A 0, A 1 ... A n} -1 for adding R _n-1 for each input and output and each connected in series ,
A moving average adding circuit MA of 2 ⁿ (= N) samples is configured.
From the moving average addition circuit MA, data of the sum of N consecutive samples among the sample data input to the input terminal T _IN is output every clock. An adder circuit FA having a positive feedback configuration for feeding an output back to an adder input terminal is connected in series with the moving average adder circuit MA.
With the above configuration, an accumulating circuit is obtained. That is, the adder circuit FA having the positive feedback configuration provides the k-sample delay pipeline adder A _FA with N-k sample delay (z- (N-
Become register R _FA of K)) are connected in series, since N sample intervals of data are sequentially cumulatively adding, cumulative data of the input data from the input terminal T _IN is obtained from the adder circuit FA. Furthermore, this in series with the adder circuit FA positive feedback configuration, and the subtraction circuit SB is connected to subtract the output from the input of the register R _SB of L sample delay, the output terminal
From T _OUT , total (moving average) data of successive L samples of the input data is obtained every clock. This addition has been used to the subtraction circuit SB unit A _SB pipeline adder likewise the k sample delay is used. The connection order of the above-described circuit units FA, MA, and SB may be interchanged. According to this accumulator circuit, N samples (N ≧ N) are obtained by using an adder that obtains an output delayed by a predetermined number of clocks k (or a delay of k samples for sample data to be handled), for example, a so-called pipeline adder. k) A positive feedback adder circuit that feeds back delayed data to the input side and adds the data, and a moving average that performs a moving average addition of N samples (an operation for obtaining a total sum of N consecutive samples for each clock). By forming an adding circuit section and connecting these adding circuit section and the moving average adding circuit section in series, it is possible to obtain an accumulating circuit for outputting a cumulative added value of the input sample data. In addition, a subtraction circuit unit for subtracting L sample delay data of the input data from the input data (that is, a circuit unit for obtaining a difference between data shifted by an arbitrary L sample) is connected in series to the accumulating circuit. , Or a moving average of the L samples (the value of the sum of successive L samples) or a moving average accumulator circuit can be obtained. D. Problems to be Solved by the Invention According to such an accumulative circuit configuration, an accumulative result can be obtained for each sample, but if it is not necessary, the circuit is redundant. In particular, when it is sufficient to obtain the sum of N samples of input data only once per N samples, the above circuit configuration can be further simplified. The present invention has been made in view of such a situation, and uses a so-called pipeline adder or the like capable of operating at high speed in time-division multiplexing to compare operations such as addition with a simple configuration. It is an object of the present invention to provide a time axis multiplexing operation circuit which can be performed at a very high speed. E. Means for Solving the Problems In order to solve the above problems, the time axis multiplexing arithmetic circuit according to the present invention comprises:
A register circuit comprising a plurality of registers connected in series, the input data register circuit comprising at least two registers to which input data is supplied connected in series, and operation output data from the computing unit being supplied A plurality of output data register circuits in which at least two registers are connected in series; at least two multiplexers for selecting output data from each register of the plurality of register circuits and sending the selected data to the arithmetic unit; A controller for controlling the operation of the plurality of register circuits and the multiplexer; obtaining time-division multiplexed output data from the register circuits by the controller; and sending the output data to a computing unit via the multiplexer. , Time-division multiplexing processing is performed by the arithmetic unit. F. Operation By using time-multiplexed arithmetic units that can operate at high speed, there is no need to provide multiple arithmetic units, and the configuration can be greatly simplified. G. Embodiment G-1. Basic Configuration of Embodiment (FIG. 1) Hereinafter, as one embodiment of the time-axis multiplexing operation circuit according to the present invention, a single adder is used for time-axis multiplexing to perform cumulative operation. An accumulator circuit for realizing addition will be described with reference to the drawings. FIG. 1 is a block diagram showing a basic configuration of an embodiment in which the present invention is applied to the above accumulating circuit. In the accumulator circuit shown in FIG. 1, an adder (a so-called pipeline adder) 11 capable of high-speed operation by performing the above-described pipeline processing is used. The adder 11 is equivalently represented as a configuration in which a k-stage register that generates a delay of k predetermined clocks (k sample delay) is added to a normal adder. This pipeline adder 11 has an input terminal T
A fast operatively sampling frequency f _s of the input data from the _IN, when the period of the sampling and _{T s (= 1 / f s} ), the delay time due to the pipelining kT _s
Becomes Then, a plurality of register circuits RR ₀ like in FIG. 1 has two registers, respectively, for example R _01, consists series circuit of R _02, such register circuit meter from RR ₀ to RR _n n
+1 are provided. Of these (n + 1) registers, the input data from the terminal T _IN is supplied to the input data register circuit RR _0, the register circuit RR for the output data
₁ ... RR _n−1 and RR _n are supplied with output data from the adder 11. Output data from the adder 11 is taken out from an output terminal T _OUT via a register R _OUT . The output data from each of the registers R _{01 to} R _{n2 in} these register circuits RR _{0 to} RR _n is selected and the adder is selected.
In order to send to 11, two multiplexers 13 and 14 are provided. The multiplexer 13 is provided for each of the register circuits RR _{0 to} RR _n
The multiplexer 14 selects the output data from one of the registers R _{01 to} R _n1 , and the multiplexer 14 selects each of the register circuits RR _{0 to} RR _n
Are connected so as to select output data from the other registers R _{02 to} R _n2 . Furthermore, the controller for controlling the operation of these register circuits RR ₀ ~RR _n and the multiplexer 13
There are twelve. The controller 12 to obtain the output data time-axis multiplexed from (the registers R ₀₁ to R _n2 in) each register circuit RR ₀ ~RR _n, an adder the output data through the multiplexer 13 and 14 11 and the adder 11 performs time axis multiplexing operation processing. Each register circuit RR _0, RR ₁ registers R ₀₁ ~ in ～RR _n
The operation of R _n2 is controlled by the controller 12, and each register circuit RR ₀ , RR ₁ ... RR _n has an independent operation speed. G-2. Equivalent circuit and basic operation of the embodiment (FIG. 2, FIG.
Here, the accumulator circuit of FIG. 1 shows an example in which a total value obtained by cumulatively adding, for example, m · 2 ⁿ samples of input data is output once per m · 2 ⁿ samples, This is what was realized by time-axis-multiplex the use of the adders a ₀ to a _n of the addition process one adder 11 of the adder circuit shown in Figure 2. In the accumulator circuit of FIG. 2, the input terminal T _IN
Sum data of m · 2 ⁿ samples of the input data supplied to the, to be output at a frequency fs / m · 2 ⁿ from the output terminal T _OUT. That is, the second figure, the n adders A ₀ to A _n-1 for adding n registers R ₀ to R _n-1 of the input data and output data and, respectively, feeding the output data to the input adder a and _n made by serially connecting cumulative circuit has been shown, each of the adders
A _{0 to An} are all the pipeline adders. Here, the delay amounts of the respective registers R ₀ , R ₁ , R ₂ ... R _n-1 are T _s , 2T _s , 4T _s ... 2 ^n-1 T _s (where T _s is the above input value). It is the sampling period) of the input data to the terminal T _iN. This is the frequency of the operation clock supplied to the clock terminal of the register R ₀ ~R _n-1 is, when both are above f _s, each register _{R 0, R 1, R 2} ··· R n-1 Are set to ¹ , 2, 4,..., 2 ⁿ⁻¹ , respectively. Next, an adder An having a so-called positive feedback configuration at the last stage
Is performs a cumulative addition by zero clear or reset at a rate of once per m · 2 ⁿ samples of the input data (m · 2 ⁿ T _s period), the output terminal
The total data of m · _2n samples is obtained from T _OUT . In FIG. 2, first, an adder A _{0 at} the first stage adds every two samples of input data supplied from the input terminal T _{IN at a} frequency f _s (period T _s = 1 / fs), and The addition data is output at a rate (cycle 2T _s , frequency f _s / 2). The adder A _{1 in the} next stage is 2T _s from the adder A _{0 in the} previous stage.
Cycle by sequentially adding every two data output (Frequency fs / 2), 4 rate of once the addition data every 4 samples of the sample of the input data (the period 4T _s, frequency fs / 4) To output. By serially connecting the adder in the same manner, the n-th adder A _n-1 th stage at a rate of once sum data of 2 ⁿ samples of the input data every 2 ⁿ samples (frequency fs / 2 ⁿ ) is output. For example, n = 3
In the case of, 2 ³ = 8 due to the configuration of the ^three -stage adders A _{0 to} A _2.
The sum data of the input data sample is to be outputted by the 8T _s period. Here Figure 3, when calculating the sum of the data d ₀ to d ₇ consecutive 8 samples of the input data, output data from each stage to the period T _s of the input data d ₀ to d ₇ is indicative of the period of the relationship, the initial stage of the adder a ₀ 2 sample added data _d 0 to 1 at 2T _s cycle _from, d 2 to _{3, d 4 to 5} and _{d 6 to 7} are sequentially obtained , 4 samples of cumulative data d _{0 to 3} and d _{4 to 7} are sequentially obtained by 4T _s period from the initial stage of the adder a _1, the sum data d ₀ of 8 samples from adder a ₂ of the third stage _{~ 7} will be obtained. It should be noted that the input data d ₈ even after the d _7,
Since d ₉ , d _10, ... are sequentially input, the sum data of the above eight samples is sequentially d _0-7 , d _8-15 , d _16-23.
..., and the they are output by the 8T _s period from adder A ₂ of the third stage. Next, generally, the sum data (frequency f _s / 2 ⁿ ) of 2 ⁿ samples of the input data obtained from the adder _{An-1 at the n-} th stage
(At the frequency f _s / 2 ⁿ⁾ the n + a 1-stage adder A _n with every other every 2 ⁿ samples of the input data is added cumulatively. The adder A _n, a rate of once every m times, i.e. at the rate of once per m · 2 ⁿ samples of the input data (at the frequency f _s / m · 2 ⁿ⁾ by zero clear or reset, the output terminal From T _OUT , total data of m · 2 ⁿ samples of input data can be obtained. For example, n = 3 and m
= 3 in the case of, the third stage of adder A ₂ from 8T _s total of 8 samples obtained at period data _d 0 to _{7, d 8 to 15}
And d _{16 to 23,} thereby obtaining the sum data d _{0 to 23} for cumulatively adding to 24 samples by the adder A ₃ of the positive feedback configuration of the fourth stage of the next (final stage). The relationship between the delay amount k of the pipeline adder 11 and the number of cumulative samples m · 2 ⁿ may be set to k = 2 ⁿ as the simplest example. ^n-1
It suffices to select k and n that satisfy <k ≦ 2 ⁿ . m is an arbitrary natural number. 2 ^n-1 when a <k <2 ^n, during the feedback loop of the adder A _n of the last stage inserted and connected registers 2 ⁿ -k-sample delay, k by pipeline processing adder A _n The cumulative addition of 2 ⁿ sample periods may be performed arbitrarily m times with the sample delay. The operating speed of the second adders A ₀ of cumulative circuit configuration shown in FIG. To A _n-1 and A _n (operating _{frequency), f s / 2~f s / 2} n and f _s /
Considering that a 2 ^n, by the time-axis-multiplex process using a single adder 11 operating at a frequency f _s, is realized cumulative circuit of FIG. 1. That is, each of the adders A ₀
Operation speed required for realizing the process of adding to A _n-1 and A _n by time-axis-multiplex the use of one adder, fs / 2 + fs / 4 + ... fs / 2 n + fs / 2 n = the frequency f _s than fs. By the way, each of the register circuits RR ₀ , RR _1.
RR _n-1 are operated at frequencies f _s , f _s / 2... F _s / 2 ⁿ in response to a control signal from the controller 12, and each of the registers R ₀ and R in FIG. ₁ ··· R _n-1 of the delay time T _s, respectively to achieve a ^{_{2T s ··· 2 n-1 T}} s. In this case, the registers R ₀₁ , R ₁₁ , R _21.
..R _{n-1 and 1} are the input from the input terminal T _IN and the adder 1
This is for taking in data at a predetermined timing with respect to the output from 1 and temporarily holding the data, and the second
The operation corresponding to each of the registers R ₀ , R ₁ , R ₂ ,..., R _n−1 in the figure is performed by the respective registers R ₀₂ , R ₁₂ , R _22.
R _n−1,2 . Incidentally, the register R _n1, R _n2 of Figure 1 is provided for timing adjustment of the input and output data when implementing the cumulative operation by the adder A _n of FIG. 2. G-3. Specific configuration and operation of the embodiment (FIG. 4, FIG.
Next, as a specific example of the accumulator circuit of the above embodiment, the configuration and operation when, for example, n = 2 and m = 3 will be proved with reference to FIGS. 4 and 5. FIG. That is, FIG. 4 is a block diagram showing an accumulator circuit in which n is 2 and m is 3 in the above embodiment of the present invention.
A four-stage register that causes sample delay) is used. Also, three register circuits RR ₀ , RR ₁ , RR
₂ is composed of two registers each, and the input terminal T _IN
The total value obtained by cumulatively adding 12 (= 3.2 ² ) samples of the input data supplied to the
An example of output from the output terminal T _{OUT (in a} period of T _s ) is shown. To the input terminal T _IN of FIG. 4, as shown in FIG. 5 A, input from the time t _o the T _s as the period data d _0, d _1,
When d ₂ ... are sequentially supplied, each multiplexer 13,
The outputs from 14 are as shown in FIGS. 5B and 5C. These outputs B and C are added in the adder 11 and delayed by the above four samples to obtain as shown in FIG. 5D. In this case, the outputs from the registers R ₀₁ and R ₀₂ of the register circuit RR _{0 in} FIG. 4 are obtained as shown in FIGS.
The outputs from the registers R ₁₁ and R _{12 of} RR ₁ are obtained as shown in FIGS. 5G and 5H, and the registers R ₂₁ and R of the register circuit RR ₂ are obtained.
The output from ₂₂ is obtained as shown in FIGS. In addition,
In the time chart of FIG. 5 A-J, shows only directly relevant data portions operation for calculating the sum data of successive 8 sample d ₀ to d ₇ from time t _o,
Other data parts with low relevance are shown in parentheses (d ₀ ) or the like, or are not shown. In these FIG. 4 and FIG. 5, the input data A is sequentially delayed by the register R ₀₁ and R ₀₂ of the register circuit RR _0, for example at the input timing of the data d ₂ of the input A, while the output E from the register R ₀₁ appearing data d _0, respectively during the output F from the data d _1, Kamata register R ₀₂ to. These data d ₁ and d ₀ is selected by each multiplexer 13 and 14, the adder 11 is a 4T _s delay addition is sent, in addition output D at the input timing of the data d ₆ input A 2 Appears as sample addition data d _0-1 . The added data d _{0 to 1} are stored in the register circuit RR
Captured by the _first register R _11, by the register R ₁₂ it is delayed the 2T _s min. Therefore, the data d _{0 to 1}
The register R12 at the input timing of the data d ₉ inputs A
In the output H of At this time, the output G of the register R ₁₁
The following two-sample added data d2 to ₃ appear therein, and the data _{d0 to 1} and d2 to ₃ are selected by multiplexers 13 and 14, respectively, and sent to the adder 11. These data _d 0 to _1, 4 sample added data _{d 0 to 3} obtained by adding the _{d 2 to 3} will appear in addition output D at the input timing of the data d ₁₃ of the input A, the register R _21, and R
The register circuit RR ₂ of ₂₂ delayed by 2T _s, input A
_At the input timing of the data d15, the multiplexer 13
The data is zero-cleared (or reset) by the zero-clear output CLR from the controller 12, and 0 data is added to the adder 11.
Is delayed by 4T _s (data d _{19 of} input A).
Output D obtained from the adder 11 at the input timing of
Is four-sample added data _d0-3 . _At the input timing of the data _d19 , the addition data _d0-3 in the addition output D is selected by the multiplexer 13 and sent to the adder 11, and the next 4 data obtained in the output C of the multiplexer 14 is output. Sample addition data d
₄ to ₇ are sent to the adder 11. Each of these data d
_0-3 and _{d 4~7} are added while being 4T _s delay,
8 samples added data d _{0 to 7} at the input timing of the input A of the data d ₂₃ is obtained. The addition data _d0 to _d7 are again selected by the multiplexer 13 and sent to the adder 11, and the next 4-sample addition data _d8 to ₁₁ obtained in the output C of the multiplexer 14 are sent to the adder 11. by being sent, it is possible to obtain further after 4T _s final 12 samples of the sum data d _{0 to 12} from adder 11. The twelve samples of total data d _{0 to} 12 are taken out from the output terminal T _OUT via the output register R _OUT . In the description the time axis multiplexing addition process described above, two samples added data _d 0 to _1, d 2 to _3, the addition operation for obtaining _{d 4 to 5} and the like is performed in the frequency fs / 2, 4 sample added data _{d 0 -3} , _d4-7, etc. are performed at the frequency fs / 4, and the 4-sample added data d
_Since the cumulative addition operation of _0-3 and _d4-7 is performed at the frequency fs / 4, the operation speed required for the adder 11 is fs / 2 + fs / 4 + fs / 4 = fs. That is, if the addition operation is performed at the frequency fs or higher, the addition operation can be realized by using one adder 11 in the time axis multiplexing. G-4. Other Embodiments Note that the present invention is not limited to the above embodiment, and for example, the number of delay stages of an adder having a delay, the number of samples to be cumulatively added, and the like can be arbitrarily set. In addition, the present invention can be applied to the time axis multiplex use of a high-speed arithmetic unit that performs various operations other than the addition operation. In addition, various changes can be made without departing from the spirit of the present invention. H. Effects of the Invention According to the time axis multiplexing arithmetic circuit of the present invention, by using time axis multiplexing of a high-speed arithmetic unit such as a so-called pipeline adder, it is possible to perform operations such as cumulative addition with a simple configuration. Can be realized.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block circuit diagram showing a basic configuration of an embodiment in which the present invention is applied to an accumulator circuit, and FIG. 2 is an equivalent accumulator circuit for explaining the operation principle of the embodiment. FIG. 3 is a block diagram showing the configuration, FIG. 3 is a time chart for explaining the basic operation of the embodiment, FIG. 4 is a block circuit diagram showing the specific configuration of the embodiment, and FIG. FIG. 6 is a block circuit diagram showing an accumulator circuit using a pipeline adder for explaining the present invention. 11 ...... pipeline adder 12 ...... controller 13 ...... multiplexer T _IN ...... input terminal T _OUT ...... output terminal RR ₀ ~RR _n ...... register circuit R ₀₁ ~R _n2, R _OUT ...... register

Claims (1)

(57) [Claims] A high-speed operation unit, an input data register circuit in which at least two registers to which input data is supplied are connected in series, and at least two registers to which operation output data from the operation unit are supplied are connected in series. A plurality of output data register circuits connected to each other, at least two multiplexers for selecting output data from each register of the plurality of register circuits and sending the selected output data to the arithmetic unit, the plurality of register circuits and the multiplexer And a controller for controlling the operation of the control circuit. The controller obtains output data multiplexed on the time axis from each of the register circuits, sends the output data to the arithmetic unit via the multiplexer, and multiplexes the time axis on the arithmetic unit. A time axis multiplexing arithmetic circuit characterized by performing arithmetic processing.