JP2943227B2 - Semiconductor memory device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an MNOS type EEPROM (Metal Nitride Oxide Se
Electronically Erasable and Programmable
ROM) The present invention relates to miniaturization and high integration of semiconductor memory devices.

(Prior art)

MNOS EEPROM is an EPROM (Erasable and Programmable)
Unlike ROM), stored information can be electrically rewritten without performing ultraviolet irradiation.

As a conventional MNOS type EEPROM semiconductor memory device, for example, there is one as shown in FIG. [See Nikkei Electronics, 1986.2.10, (No. 338), PP142-145] This semiconductor memory device comprises a first gate insulating film 3 made of an oxide film having a thickness capable of directly tunneling electrons and a nitride film. A first gate electrode region for storing information including the second gate insulating film 4 and the store gate electrode 5, and stored information including the third gate insulating film 6, the isolation gate electrode 7, and the select gate electrode 8. , And a source region 10 and a drain region 11.

FIG. 11 shows an N-type semiconductor substrate 1, second and third gate electrode regions formed on the surface of a P-well 2 which is a P-type impurity region formed in the N-type semiconductor substrate 1, and second and third gate electrode regions. A first gate electrode region formed on the surface of the P well 2 between the third gate electrode regions at a predetermined interval, and a source formed in the P well 2 outside the second and third gate electrode regions. 4 is a cross-sectional view of a semiconductor memory device including a region 10 and a drain region 11. FIG.

The operation of storing and reading information in the conventional semiconductor memory device will be described.

Information storage operation With a predetermined voltage applied to the source region 10 and the drain region 11 and a negative voltage applied to the isolation gate electrode 7 and the P well 2, a positive voltage is applied to the store gate electrode 5 and the select gate electrode 8. Is applied, electrons existing on the connection surface between the first gate insulating film 3 and the second gate insulating film 4 directly tunnel through the first gate insulating film 3 and move in the P well 2, so that the first gate insulating film 3 Electrons on the connection surface between the film 3 and the second gate insulating film 4 are lost, and a hole is formed. In this manner, information is stored by storing positive charges in the first gate electrode region.

Erasing Operation of Stored Information With the same positive voltage applied to the source region 10, the drain region 11, the P well 2, the isolation gate electrode 7 and the select gate electrode 8, When a voltage is applied, electrons are directly tunneled from the P well 2 through the first gate insulating film 3, so that electrons are supplied to holes existing on the connection surface between the first gate insulating film 3 and the second gate insulating film 4. Is done. As a result, the charge stored in the first gate electrode region disappears, and the stored information is erased.

Read operation of stored information When a positive voltage is applied to the drain region 11 and the same positive voltage is applied to the isolation gate electrode 7 and the select gate electrode 8 with the store gate electrode 5 and the P well 2 being grounded. When a positive charge is accumulated in the first gate electrode region, the source region 10 to the drain region
11 are electrically connected to each other by a channel formed in the P well 2, but when no positive charge is accumulated in the first gate electrode region, the P well 2 immediately below the first gate insulating film 3 is formed.
Since no channel is formed in the inside, the source region 10 and the drain region 11 are not electrically connected. Therefore, the stored information can be read by looking at the current flowing between the source region 10 and the drain region 11.

Next, a manufacturing process of the conventional semiconductor memory device will be described.

P-type impurity is diffused into N-type semiconductor substrate 1 to form P-well 2
Is formed, and the surface of the P well 2 is oxidized to form a third gate insulating film 6, and an isolation gate electrode 7 and a select game electrode 8 are formed on the surface of the third gate insulating film 6 at predetermined intervals. And the isolation gate electrode 7
And oxidizing the surface of select gate electrode 8 to form interlayer insulating film 9, removing third gate insulating film 6 and interlayer insulating film 9 between isolation gate electrode 7 and select gate electrode 8, and removing third gate insulating film 9. A first gate insulating film 3 made of an oxide film having a thickness capable of directly tunneling electrons is formed on the surface of the P well 2 where the insulating film 6 and the interlayer insulating film 9 have been removed, and the surface of the first gate insulating film 3 is formed. A second gate insulating film 4 made of a nitride film is formed on the second gate insulating film 4, a store gate electrode 5 is formed on the surface of the second gate insulating film 4, and the P gate 2 is formed outside the isolation gate electrode 7 and the select gate electrode 8. A source region 10 and a drain region 11 are formed by diffusing an N-type impurity to manufacture a semiconductor memory device.

[Problems to be solved by the invention]

In the conventional semiconductor memory device described above, since the first, second, and third gate electrode regions are provided on the flat surface of the P well 2, the structure between the source region 10 and the drain region 11 is widened. There is a problem.

In addition, the first gate electrode region cannot be formed in a self-aligned manner with respect to the second and third gate electrode regions (formed without using a mask for alignment), so that a margin for mask alignment is provided. There is a manufacturing problem that it is necessary to take a sufficient amount.

As described above, structural and manufacturing problems have hindered miniaturization and high integration of semiconductor memory devices.

[Means for solving the problem]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and has a semiconductor memory device having a semiconductor substrate having a convex portion on its surface, and a first gate electrode region formed on the upper surface of the convex portion of the semiconductor substrate. And a second and third gate electrode region formed to face the side wall of the projection of the semiconductor substrate.

After forming the first gate electrode region on the semiconductor substrate,
Forming a convex portion on the semiconductor substrate such that the first gate electrode region remains on the upper surface of the convex portion, and forming a second and a third gate electrode region facing the side wall of the convex portion of the semiconductor substrate; To manufacture.

[Action]

The structure of the semiconductor memory device is a semiconductor substrate having a convex portion on the surface, a first gate electrode region formed on the upper surface of the convex portion of the semiconductor substrate, and a second and a second formed on the side wall of the convex portion of the semiconductor substrate. Because of the structure including the three gate electrode regions, the channels formed in the semiconductor substrate by the first, second, and third gate electrode regions are formed three-dimensionally on both sides of the upper surface and the side wall of the protrusion of the semiconductor substrate. In addition, the distance between the source region and the drain region can be reduced without changing the effective channel length.

After forming the first gate electrode region on the semiconductor substrate, a convex portion is formed on the semiconductor substrate such that the first gate electrode region remains on the upper surface of the convex portion, and the second and second gate electrode regions are opposed to the side walls of the convex portion of the semiconductor substrate. Since the third gate region was formed,
The first gate electrode region can be formed in a self-aligned manner with respect to the second and third gate electrode regions, and a margin for mask alignment between the second and third gate electrode regions becomes unnecessary. For the above reasons, the above problem can be solved.

〔Example〕

 Hereinafter, description will be made based on specific examples.

FIG. 1 is a diagram showing a first embodiment of the present invention.
In FIG. 1, reference numeral 1 denotes an N-type semiconductor substrate.
A P-well 2 is formed in a semiconductor substrate 1, and a projection is formed on the surface of the P-well 2. On the upper surface of the convex portion on the P well 2, there are formed a first gate insulating film 3 made of an oxide film having a thickness capable of directly tunneling electrons, a second gate insulating film 4 made of a nitride film, and a store gate electrode 5. First
A gate electrode region is formed, and a second gate electrode region including a third gate insulating film 6 and an isolation gate electrode 7 is formed on the left side of the side wall of the protrusion on the P well 2. A third gate electrode region including a third gate insulating film 6 and a select gate electrode 8 is formed on the right side of the side wall of the upper convex portion. A drain region 11 is formed.

Next, the operation of the first embodiment will be described with reference to FIG. Basically, the operation is the same as that of the conventional example shown in FIG. 11, but when the same positive voltage is applied to the isolation gate electrode 7 and the select gate electrode 8 when reading the stored information, A channel formed in the P well 2 where the select gate electrode 7 and the select gate electrode 8 are in contact with each other via the third gate insulating film 6 extends from the side wall portion of the protrusion on the P well 2 to the lower outer portion of the protrusion on the P well 2. It becomes three-dimensional, and from the source region 10 to the drain region 11
Is formed along the convex portion on the P-well 2.

Since each of the three gate electrode regions has a three-dimensional structure formed on the protrusion provided on the semiconductor substrate, the channel formed in the P well 2 by each gate electrode region also has a three-dimensional structure. Source area 10 without changing
And the interval between the drain region 11 can be reduced.

Next, the manufacturing method of the first embodiment will be described with reference to the drawings shown in FIGS. 2 to 5 are cross-sectional views of the semiconductor memory device showing the manufacturing steps of the first embodiment.

1) As shown in FIG. 2, a P-type impurity is diffused into an N-type semiconductor substrate 1 to form a P-well 2, and a first gate insulating film 3 made of an oxide having a thickness capable of directly tunneling electrons. Is formed by oxidizing the surface of the N-type semiconductor substrate 1 and the second gate insulating film 4 made of nitride is formed on the surface of the first gate insulating film 3.
Is formed by the CVD method, and a store gate electrode 5 made of polycrystalline silicon is formed on the surface of the second gate insulating film 4 by the CVD method.

2) As shown in FIG. 3, the surface of the P well 2 is raised by anisotropic etching, for example, a reactive ion etching (RIE) method, while leaving a necessary portion of the store gate electrode 5 on the upper surface of the projection. Formed in the part. Here, the size of the height B of the convex portion is set to be equal to the height B because it is necessary to secure a space between the channel formed when electric charges are accumulated in the first gate electrode region and the source region 10 and the drain region 11. Is determined, and the upper limit of the height B is determined from the problem of wiring passing over the convex portion and the problem of structural strength. For this reason, for example, when the length A of the upper surface of the projection is 2 μm, the height B is 1 to 2
A convex portion is formed to have a thickness of μm.

3) As shown in FIG. 4, the entire surface of the N-type semiconductor substrate 1 is oxidized to form a third gate insulating film 6, and polycrystalline silicon is formed on the entire surface of the third gate insulating film 6 by a CVD method. RIE
By removing unnecessary polycrystalline silicon by the method, the isolation gate electrode 7 and the select gate electrode 8 are formed.

4) As shown in FIG. 5, the surfaces of the isolation gate electrode 7 and the select gate electrode 8 are oxidized to form an interlayer insulating film 9, and the source region 10 outside the isolation gate electrode 7 and the select gate electrode 8 is formed. After removing the third gate insulating film 6 at the portion where the third gate insulating film 6 is to be formed, the N-type impurity is diffused into the P well 2 from the portion where the third gate insulating film 6 has been removed to form the source region 10 and the drain region 11. To form

If the semiconductor memory device is manufactured in the above-described process, after forming the first gate electrode region on the semiconductor substrate, the convex portion is formed on the semiconductor substrate so that the first gate electrode region remains on the upper surface of the convex portion. Since the second and third gate electrode regions are formed to face the side walls of the convex portion, the first gate electrode region can be formed in a self-aligned manner with respect to the second and third gate electrode regions. A margin for mask alignment between the second and third gate electrode regions becomes unnecessary. Therefore, miniaturization and high integration of the semiconductor memory device can be achieved.

FIG. 6 shows a second embodiment. The second embodiment is the sixth embodiment.
As shown in the drawing, the source region 10 is formed below the second gate electrode region, and the drain region 11 is formed below the third gate electrode region.

By forming the source region 10 and the drain region 11 below the second and third gate electrode regions, respectively,
The distance between the source region 10 and the drain region 11 can be further reduced, and miniaturization and high integration of the semiconductor memory device can be achieved.

Next, the manufacturing method of the second embodiment will be described with reference to the drawings shown in FIGS. 7 and 8 are cross-sectional views of the semiconductor memory device showing the manufacturing steps of the second embodiment.

The steps up to the formation of the projections on the surface of the P well 2 in the N-type semiconductor substrate 1 by the RIE method are the same as the steps 1) and 2) shown in the first embodiment.

3) As shown in FIG. 7, an N-type impurity is diffused outside the convex portion on the surface of the P well 2 to form a source region 10 and a drain region 11.
Is formed, and the entire surface of the N-type semiconductor substrate 1 is oxidized to form a third gate insulating film 6.

4) As shown in FIG. 8, after forming polycrystalline silicon on the surface of the third gate insulating film 6 by the CVD method, unnecessary portions of the polycrystalline silicon are removed by the RIE method to remove the isolation gate electrode 7 and the select gate electrode 8. Is formed, and the surfaces of the isolation gate electrode 7 and the select gate electrode 8 are oxidized to form an interlayer insulating film 9.

Also in the case where the semiconductor memory device is manufactured in the above-described steps, the same effect as in the case where the semiconductor memory device is manufactured in the step shown in the first embodiment can be achieved, and miniaturization and high integration of the semiconductor memory device can be achieved.

FIG. 9 shows a third embodiment. In the third embodiment, an N-type semiconductor substrate 1 having a convex portion provided on the surface of a P-well 2 serving as a P-type impurity region, and a third type formed to face a side wall of the convex portion of the N-type semiconductor substrate 1. N-type semiconductor substrate 1, second and third gate electrode regions including gate insulating film 6, isolation gate electrode 7 and select gate electrode 8.
A first gate electrode comprising a first gate insulating film 3, a second gate insulating film 4, and a store gate electrode 5 formed on the upper surface of the convex portion so as to partially overlap the isolation gate electrode 7 and the select gate electrode 8. 1 shows a semiconductor memory device including a region, a source region 10, and a drain region 11.

The structure of the embodiment shown in FIG. 3 is almost the same as the structure of the first embodiment. Since the channel formed in the P well 2 is three-dimensional, the source region 10 and the drain are formed without changing the effective channel length. The interval between the regions 11 can be reduced.

If the source region 10 and the drain region 11 are formed below the isolation gate electrode 7 and the select gate electrode 8, respectively, as in the second embodiment, the same effects as in the second embodiment can be obtained. .

FIG. 10 shows a fourth embodiment. In the fourth embodiment, an N-type semiconductor substrate 1 in which a groove (recess) is provided on the surface of a P-well 2 that is a P-type impurity region, and a N-type semiconductor substrate 1 formed to face a side wall of the groove in the N-type semiconductor substrate 1. The second and third gate electrode regions including the third gate insulating film 6, the isolation gate electrode 7 and the select gate electrode 8, and the isolation gate electrode 7 and the select gate electrode 8 are formed at the bottom of the groove of the N-type semiconductor substrate 1. A semiconductor memory device comprising a first gate electrode region including a first gate insulating film 3, a second gate insulating film 4, a store gate electrode 5, a source region 10, and a drain region 11, which are formed to partially overlap each other. Is shown.

The fourth embodiment has a structure in which the first, second and third gate electrode regions are formed in a groove (recess) provided in the N-type semiconductor substrate 1, so that the channel formed in the P well 2 is three-dimensional. Source region without changing the effective channel length
The interval between 10 and the drain region 11 can be reduced.

Although the present invention has been described based on the specific embodiments, the present invention is not limited to the above-described embodiments, but may be as follows.

 The conductivity type of each semiconductor region may be reversed.

The material of each gate electrode and the third gate insulating film may be appropriately changed depending on the use conditions and the like.

An impurity may be introduced into a channel portion formed in the substrate for controlling a threshold value.

When a plurality of semiconductor storage devices are formed on a substrate, the projections of the semiconductor substrate may be formed independently for each semiconductor storage device, or may be formed in units of several semiconductor storage devices.

The side wall of the convex part of the semiconductor substrate is
Uprighting at 90 ° was most effective. However, if the second and third gate electrodes can be formed in a self-aligned manner with respect to the projections of the semiconductor substrate, the second and third gate electrodes need not be upright at 90 °.

〔The invention's effect〕

As described above with reference to the specific examples, the semiconductor substrate having the convex portion on the surface, the first gate electrode region formed on the upper surface of the convex portion of the semiconductor substrate, and the side wall of the convex portion of the semiconductor substrate. Since the structure includes the second and third gate electrode regions formed together, the distance between the source region and the drain region can be reduced, and the area occupied on the semiconductor substrate can be reduced. Further, after forming the first gate electrode region on the surface of the semiconductor substrate, a convex portion is formed on the semiconductor substrate so that the first gate electrode region remains on the upper surface of the convex portion. Since the step of forming the gate electrode region is performed, the first gate electrode region can be formed in a self-aligned manner with respect to the second and third gate electrode regions, and the mask alignment margin between the second and third gate electrode regions can be increased. Become useless. Therefore, there is an effect that the semiconductor memory device can be miniaturized and highly integrated.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view showing a first embodiment of the present invention, and FIGS. 2 to 5 are sectional views of a semiconductor memory device showing manufacturing steps of the first embodiment. 6, FIG. 6 is a cross-sectional view showing a second embodiment of the present invention, FIGS. 7 and 8 are cross-sectional views of a semiconductor memory device showing manufacturing steps of the second embodiment, and FIG. FIG. 10 is a sectional view showing a third embodiment of the present invention, FIG. 10 is a sectional view showing a fourth embodiment of the present invention, and FIG. 11 is a conventional view. DESCRIPTION OF SYMBOLS 1 ... N-type semiconductor substrate, 2 ... P well, 3 ... 1st gate insulating film, 4 ... 2nd gate insulating film, 5 ... Store gate electrode, 6 ... 3rd gate insulating film, 7 ... ... Isolation gate electrode, 8 ... Select gate electrode, 9 ...
Interlayer insulating film, 10 source region, 11 drain region.

Claims (2)

(57) [Claims] A semiconductor substrate having a source region, a drain region, and first, second and third gate electrode regions, wherein information is stored in the first gate electrode region; A semiconductor memory device for reading information stored in a gate electrode region, comprising: a semiconductor substrate having a convex portion on a surface; the first gate electrode region formed on an upper surface of the convex portion of the semiconductor substrate; The second portion formed facing the side wall of the convex portion of the second portion.
And a third gate electrode region. 2. A semiconductor substrate having a source region, a drain region, and first, second, and third gate electrode regions, wherein information is stored in the first gate electrode region; In a method for manufacturing a semiconductor memory device for reading information stored in a gate electrode region, a step of forming the first gate electrode region on the semiconductor substrate, wherein the first gate electrode region is formed on an upper surface of a projection. A semiconductor memory, comprising: forming a convex portion on the semiconductor substrate so as to remain; and forming the second and third gate electrode regions facing a side wall of the convex portion of the semiconductor substrate. Device manufacturing method.