JP2825205B2 - Encryption device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encryption device that obtains a ciphertext from plaintext and obtains a plaintext from ciphertext using an encryption key as a parameter.

"Prior Art" A conventional encryption device is disclosed in, for example, Japanese Patent Application No. 62-308463 "Encryption Device", and includes an encryption processing unit and a key processing unit. As shown in FIG. 11, plaintext (or ciphertext) is input as input data to the encryption processing unit, and an encryption key (intermediate key) processed by the key processing unit is input as a parameter. The ciphertext (or plaintext) is output through a diffusion processing stage provided in a specific manner. As shown in FIG. 12, the key processing unit corresponding to the encryption processing unit receives the encryption key as input data, and outputs an intermediate key through eight consecutive diffusion processing stages.

For example, in an encryption device having four encryption stages in the encryption processing unit, compared to an encryption device having eight diffusion stages, the encryption time required to create a ciphertext and the encryption time required to create an original plaintext from a ciphertext are compared. The decoding time is reduced. That is, the encryption speed and the decryption speed increase. Conversely, in an encryption device having 16 diffusion processing stages, for example, the encryption speed and the decryption speed are lower than in an encryption device having 8 diffusion processing stages. Generally, it is known from experience that the encryption strength increases as the number of diffusion processing stages increases, so it can be said that it is better to increase the number of processing stages from the standpoint of emphasizing encryption strength. On the other hand, there is a method of using an encryption device that does not require much encryption strength, but wants to improve the speed of encryption and decryption.For example, it is necessary to check whether data has been falsified by performing data compression in the encryption device. There are techniques used to make decisions. This technique is called "data integrity" and is shown, for example, in the international standard ISO9797 (data integrity). Since only the data randomization function in ciphertext generation is used here, the strength of encryption is not emphasized.

The conventional encryption device is characterized in that the number of continuations of the diffusion processing stage of the encryption processing unit is fixed. Therefore,
Use for both applications where you want to increase the number of diffusion processing stages in the encryption device and increase the encryption strength, and for other applications where you want to reduce the number of diffusion processing stages and use them faster. And there is a problem that it is not possible to flexibly respond to requests for each purpose of use.

[Means for Solving the Problems] According to the present invention, by providing the number-of-spreading-processing-stages control unit, the number of spreading processing stages of the encryption processing unit of the encryption device is made variable, and the key processing unit is set according to the set number of repetitions. , The performance (encryption speed and decryption speed) required for each use environment of the encryption device can be handled.

Embodiment 1 As shown in FIG. 1, in the encryption processing unit, plaintext or ciphertext is input as input data, and the encryption key (intermediate key) processed by the key processing unit is input as a parameter. The stage number control data N is stored in the diffusion process stage number controller 300.
, And the number-of-spread-processing-stages control unit 300 outputs a control signal 310 for controlling the number of encryption processing stages and a control signal 311 for controlling the number of key processing units. The encryption processing stage number control signal 310 is input to the spread processing stage 68 and serves as a control signal for repeating the spread processing stage 68 N times. Further, the key processing unit stage number control signal 311 is input to the spreading processing stage 76 of the key processing unit, and the spreading processing stage 76 is set to ((N / 2) +
4) Acts as a control signal for repeating it many times.

The encryption processing unit converts the 64-bit input data (plaintext or ciphertext) into an exclusive OR circuit (hereinafter referred to as an XOR circuit) 66
And the 64-bit parameter data (intermediate key) P _N , P _{N + 1} ,
An exclusive OR operation is performed on P _{N + 2} and P _{N + 3,} and the output is input to a data spreading unit 89, where the data is divided into 32-bit left data and right data by a dividing unit 67. Here, N is the stage number control data described above. The left data is directly input to the first stage of the spreading means 68 as left data, and the left data and the right data are subjected to an exclusive OR operation in the XOR circuit 69, and the output of the XOR circuit 69 is subjected to diffusion processing as right data. It is supplied to the first stage of the means 68.

In each diffusion processing stage 68, the input right data is output as it is as left data to the next diffusion processing stage 68, and is also input to the data diffusion means 71 and data is spread by 16-bit parameter data (intermediate key). The spread data is subjected to an exclusive OR operation with the left data in the XOR circuit 72, and the output of the XOR circuit 72 is output to the next spreading processing stage 68 as right data. The function of this diffusion processing stage 68 is used N times repeatedly, and similar processing is performed in each diffusion processing stage 68.

The right data of the output of the final diffusion processing stage 68 is
Is supplied as the left data of the combining means 73, and the left data of the output of the final diffusion processing stage 68 and the XOR circuit 74
, An exclusive OR operation is performed, and the output of the XOR circuit 74 is supplied to the combining means 73 as right data. The combining means 73 combines the left data and the right data as 64-bit data. The combined 64-bit data is 64-bit parameter data (intermediate key) P _{N + 4} , P _{N + 5} , P _{N + 6} , P
_The exclusive OR operation is performed by the _{N + 7} and the XOR circuit 75, and the result is output as spread output data, that is, cipher text (or decrypted text).

Next, FIG. 2 shows a key processing unit corresponding to the encryption processing unit shown in FIG. First, the input data having a length of 64 bits, that is, the encryption key, is divided into 8-bit units by the parity check circuit 65 and subjected to a parity check. However, the parity check circuit 65 may be omitted. The 64-bit encryption key output from the parity check circuit 65 is divided into 32-bit left data and right data by the dividing means 67, and is input to the first stage of the cascade arrangement of the plurality of spreading processing stages. In each diffusion processing stage 76, the right data is output as it is as left data to the next diffusion processing stage and is also supplied to the XOR circuit 77. Using the output of the XOR circuit 77 as a parameter, the data spreading means 78 performs data spreading processing on the left data, and outputs the output of the data spreading means 78 as right data to the next spreading processing stage 76. XOR circuit 77 receives the appropriate constant D ₀ In the first stage of the diffusion process stage 76, the other diffusion processing stage to enter the front of the left data. Each diffusion processing stage
The 32-bit output data of the data spreading means 78 is output as an intermediate key. This spreading processing stage 76 is controlled by the key processing unit stage number control signal 311 and is used repeatedly ((N / 2) +4) times, and the same processing is performed in each spreading processing stage 76. As a result, 64-bit input data (encryption key) is data-spread, and intermediate keys P _{0 to} P _{N + 7} are obtained by lengthening the data to (16 × (N + 8)) bits. That is, each of the 32 bits sequentially obtained from the first stage of the diffusion processing stage 76 is converted into 16 bits P ₀ , P ₁ ,
P _2, P _3, ..., and _{P N + 4, P N +} 5, P N + 6, P N + 7. This intermediate key
P ₀ , P ₁ , P ₂ , P ₃ ,..., P _N-2 , P _N-1 are respectively given as parameters from the first stage of the diffusion processing stage 68 in FIG.
XOR circuit 6 using P _N , P _{N + 1} , P _{N + 2} , P _{N + 3} , as parameter data
6 and the intermediate keys P _{N + 4} , P _{N + 5} , P _{N + 6} , and P _{N + 7} are supplied as parameter data to the XOR circuit 75, and when plain text is input to the XOR circuit 66, it is encrypted by the XOR circuit 75. The sentence is obtained. When decrypting,
The cipher text is input to the XOR circuit 66, and the intermediate keys P _N-1 , P _N-2 P _N-3 , P
_N-4 ,..., P ₁ , P ₀ are respectively given as parameter data in order from the first stage of the diffusion processing stage 68 in FIG.
Input the intermediate keys P _{N + 4} , P _{N + 5} , P _{N + 6} , P _{N + 7} to the XOR circuit 75 and the intermediate keys P _N , P _{N + 1} , P _{N + 2} , P _{N + 3} to the XOR circuit 75 XOR
A plain text (decrypted text) is obtained from the circuit 75. The order of the parameters for encryption and decryption described above is changed by the parameter order changing unit 80 in accordance with the designation of the encryption / decryption switching control signal 79.

(Diffusion processing stage of encryption processing unit) The diffusion processing stage of the encryption processing unit will be supplementarily described with reference to FIG.

In FIG. 3, selectors 100-1 and 100-2 and registers 101-1 and 101-2 used as delay means are added to one diffusion processing stage 68 in FIG. Register 10
1-1 and the register 102-2 have a function of storing left data and right data, respectively, which are output from the diffusion processing stage 68. The left data output and the right data output output from each of the registers 101-1 and 101-2 become the left data input and the right data input, respectively, via the selectors 100-1 and 100-2 in the next repetition processing. When the diffusion processing stage 68 is used for the first time (that is, first), each selector 100-1 and 1
00-2 inputs the left data of the dividing means 67 and the output of the XOR circuit 69, and when the diffusion processing stage 68 is used repeatedly, the left data output and the right data output are input again. At the end of the iterative process, the output of the diffusion stage 68 is
The right data is output to the combining means 73 and the left data is output to the XOR circuit 74 via.

The encryption processing stage number control signal 310 repeats the process of the spreading stage 68 N times.

(Diffusion Processing Stage of Key Processing Unit) The diffusion processing stage of the key processing unit will be supplementarily described with reference to FIG.

FIG. 4 adds selectors 103-1 and 103-2 and registers 104-1, 104-2 and 105 used as delay means to one spreading processing stage 76 in FIG. 2. The registers 104-1 and 104-2 have a function of storing left data and right data output from the diffusion processing stage 76, respectively. Register 105 just before the use of diffusion treatment stage 76 to the first time (i.e., initially) is left to input constants D _0. The diffusion processing stage 76
When using for the first time (i = 1, 2,..., N / 2 + 4), first, the output of the register 105 is input to the XOR circuit 77, and then the selector 103
The output of -1 is stored in the register 105 (the data is separated so as not to cause confusion). Each register
The left data output and the right data output stored in 104-2 and 104-1 are used as selectors 103-1 and 103-1, respectively, as a left data input and a right data input in the next processing of the diffusion processing stage 76.
-2. When the spreading processing stage 76 is used for the first time, the selectors 103-1 and 103-2 receive the left data output and the right data output of the dividing means 67, respectively. The key processing unit stage number control signal 311 repeats the diffusion processing stage 76 ((N / 2) +4) times.

(Data Spreading Means 71) The data spreading means has a property that even if any one bit of the input data changes, about half of the output bits change on average. FIG. 5 is a diagram for explaining the data spreading means 71, and schematically shows a data spreading means for obtaining 32-bit spread output data from 32-bit input data. Here, the parameter is 16 bits. Fifth
In the figure, 32-bit input data R is divided into 8-bit data R0, R1, R2, R3. Pn-L and Pn-R are the left half and the right half of the parameter Pn, respectively, and are both 8 bits. Is an exclusive OR corresponding to bits, and
Input and calculate two bytes (8 bits). Here, Sδ (δ is 0 or 1) of the circuit 40 is obtained by inputting its two inputs to a,
Assuming that b, w obtained as w = a + b + δmod256,
This means that 8-bit data is obtained by performing a 2-bit leftward cyclic shift. The processing result of the circuit 40 described above is indicated by S (a, b, δ).

First, the 32-bit input data R is divided into 1-byte data R0, R1, R2, and R3. Each processing block is sequentially processed according to the processing procedure described below, and is finally output as 32 bits. The symbol ← in the following equation indicates that the right side is newly calculated as the left side data after the operation.

<Processing procedure> R1 ← R1Pn−LR0 R2 ← R2Pn−RR3 R1 ← S (R1, R2,1) R2 ← S (R2, R1,0) R0 ← S (R0, R1,0) R3 ← S (R3, R3 R2,1) With such a structure, even if any one bit of the input data R changes, the bit in each one byte of the 4-byte output of the data spreading means 71 always changes.

(Data Spreading Means 78) FIG. 6 is a diagram for explaining the data spreading means 78, and schematically shows a data spreading means for obtaining 32-bit output data from 32-bit input data. . Here, the parameter is 32 bits. In FIG. 6, the 32-bit input data R is an 8-bit data R
It is divided into 0, R1, R2, and R3. 32-bit parameter PPn
Is divided into four equal parts of 8 bits each, and from the left, PPn-0, PPn-
1, represented by PPn-2 and PPn-3. Here, Sδ of the circuit 40 is the same as that included in the data spreading means 71.

First, the 32-bit input data R is divided into 1-byte processing data R0, R1, R2, and R3. Each piece of processing data is sequentially processed according to the processing procedure described below, and is finally output as 32 bits.

<Processing procedure> R1 ← R1R0 R2 ← R2R3 R1 ← S (R1, (R2PPn-0), 1) R2 ← S (R2, (R1PPn−1), 0) R0 ← S (R0, (R1PPn−2), 0) R3 ← S (R3, (R2PPn-3), 1) (Supplementary explanation of the function of the first embodiment using mathematical expressions) (Notation) (1) Block: A, Ar... Is a (multiple byte) block Represents

(2) Byte: Aj, Arj represents the j-th (j = 0, 1,...) 1 byte in block A, Ar.

(3) Concatenation: (A, B,...) Represents concatenation of data in this order.

(4): AB represents an exclusive OR corresponding to bits of blocks A and B.

(5) Φ: represents a 4-byte block with zero components.

(6) Equal sign: Indicates that the right side is substituted for the left side.

(Function) First, the function used in the description will be described.

Function S: Sδ (X1, X2, δ) = Rot2 (W) W = X1 + X2 + δmod256 X1 and X2 are 1-byte blocks. δ is a constant of 0 or 1. W is a one-byte block obtained by calculating X1 + X2 + δmod256 by regarding X1 and X2 as binary non-negative integers.

Rot2 (W) is a 1-byte block obtained by rotating the 1-byte block W left by 2 bits (rotating left by 2 bits).

Example 1: When X1 = 00010011, X2 = 11110010, δ = 1, W =
00000110 Example 2: Rot2 (11011100) = 01110011 The function f R is divided into four equal parts, and R0, R1, R2, and R3 are shown from the left, and Pn is 2
Equally divided and expressed by Pn-L and Pn-R from the left.

 f (R, Pn) is calculated in the following order.

R1 ← R1Pn−LR0 R2 ← R2Pn−RR3 R1 ← S (R1, R2,1) R2 ← S (R2, R1,0) R0 ← S (R0, R1,0) R3 ← S (R3, R2,1) The function f is realized by the data spreading means shown in FIG.

The function f R is divided into four equal parts, represented by R0, R1, R2, R3 from the left, and PPn
Equally divided and represented by PPn-0, PPn-1, PPn-2, PPn-3 from the left. f _k (R, PPn) is calculated in the following order.

R1 ← R1R0 R2 ← R2R3 R1 ← S (R1, (R2PPn-0), 1) R2 ← S (R2, (R1PPn-1), 0) R0 ← S (R0, (R1PPn-2), 0) R3 ← S (R3, (R2PPn-3), 1) The function _fk is realized by the data spreading means shown in FIG.

(Key processing) From a 64-bit encryption key, an intermediate key P _i (i = 0 to (N +
7), calculation for each 2 bytes) is performed. When including a parity bit in the encryption key, 8 ×
n, where 1 ≦ n ≦ 8 (where the bit positions are counted from left to right of the encryption key as 1, 2,...) in units of 1 byte, and then the values of these parity bits are set to zero. Change to

Let A ₀ and B ₀ be the left and right sides of the encryption key. First, let D ₀ = Φ. Subsequently, for r = 1 to N, P _i (i = 0 to (N +
7)) is determined.

_Dr = _{Ar-1 Ar} = _{Br-1 Br} = _fk ( _Ar-1 , _Br-1 , _Dr-1 ) P2 _(r-1) = ( _Br0 , _Br1 ) _{P 2 (r-1) +1} = however _{(B r2, B r3),} a r, B r, D r is an auxiliary variable. B _r0 , B _r1 , B _r2 ,
B _r3 divides a 4-byte length Br into four equal parts, and each 1 from the left
Represents a byte. The key processing unit is shown in FIG.

(Encryption procedure by the cryptographic processing unit) A 4-byte block on each of the left and right sides of the plaintext block
As L ₀ , R ₀ , first, (L ₀ , R ₀ ) = (L ₀ , R ₀ ) (P _N , P _{N + 1} , P _{N + 2} , P _{N + 3} ,) (L ₀ , R ₀ ) = (L ₀ , R ₀ ) (Φ, L ₀ ) Then, for r = 1 to N, R _r and L _r are sequentially calculated.

R _r = L _r−1 f (R _r−1 , P _r−1 ) L _r = R _r−1 Next, for R _N , L _N , (R _N , L _N ) = (R _N , L _N ) (Φ, R _N ) (R _N , L _N ) = (R _N , L _N ) (P _{N + 4} , P _{N + 5} , P _{N + 6} , P _{N + 7} ) The encryption block is (R _N , L _N ).

(Decryption procedure by the cryptographic processing unit) A 4-byte block on each side of the ciphertext block
R _N, as L _{N, first, (R N, L N)} = (R N, L N) (P N + 4, P N + 5, P N + 6, P N + 7) (R N, L _N ) = (R _N , L _N ) (Φ, R _N ) Then, for r = N〜1, L _r−1 and R _r−1 are sequentially calculated.

L _r-1 = R _rf (L _r , P _r-1 ) R _r-1 = L _r Finally, for L ₀ , R ₀ , (L ₀ , R ₀ ) = (L ₀ , R ₀ ) (Φ, L ₀ ) (L ₀ , R ₀ ) = (L ₀ , R ₀ ) (P _N , P _{N + 1} , P _{N + 2} , P _{N + 3} ) The plain text block is (L ₀ , R ₀₎ ).

(Effect of the Invention) As described above, by giving the number N of diffusion processing stages of the encryption processing unit as a variable parameter, the number of diffusion processing stages of the encryption processing unit and the key processing unit is made variable, and high-speed processing is required. In this case, it is possible to set N to a small value (for example, N = 4), and to set N to a large value (for example, N = 16) when safety is emphasized.

Example 2 This will be described with reference to FIG. In the encryption processing unit 200, a plaintext (or an encrypted text) is input as input data, and the encryption key (intermediate key) processed by the key processing unit 210 is input as a parameter. The stage number control data N is input to the spreading stage number control unit 400, and the spreading stage number control unit 400 outputs an encryption stage number control signal 410 and a key processing unit stage number control signal 411. The encryption processing unit stage number control signal 410 is input to the diffusion processing stage 202 of the encryption processing unit 200 and functions as a control signal for repeating the processing of the diffusion processing stage 202 N times. Further, the key processing section number control signal 411 is transmitted to the diffusion processing section 212 of the key processing section 210.
And serves as a control signal for repeating the diffusion processing stage 212 N times. The input data to the encryption processing unit 200 is input to the diffusion processing stage 202 via the pre-processing unit 201, where the data is subjected to N-times repetition processing, and then output via the post-processing unit 203. In the key processing unit 210, the encryption key is input and processed by the key preprocessing unit 211, and then subjected to N times of repetition processing in the diffusion processing stage 212. At this time, the i-th output parameter PP _i of the diffusion processing stage 212 of the key processing unit 210 is output, and this parameter PP _i is output to the i-th diffusion processing stage 202 of the encryption processing unit 200.
Is input to Here, i = 1, 2,..., N.

A supplementary explanation will be given with reference to FIGS. 1, 2 and 8. In FIG. 1, the XOR circuit 66 is deleted, and the input data is directly input to the dividing means 67. Similarly, the XOR circuit 75 is deleted, and the output of the combining means 73 is directly used as output data. Data diffusion means
Instead of 71, a data spreading means 71-1 shown in FIG. 8 is used. Data spreading means 71-1 is a 32-bit length parameter
The point at which PP _i (i = 1, 2,..., N) is input is the data diffusion means 71.
This is a different feature. The pre-processing unit 201 includes the dividing unit 67 and the XOR
This corresponds to the one including the circuit 69. The diffusion processing stage 202
Corresponds to the diffusion stage 68. The post-processing unit 203 includes the intersection unit 99
And the XOR circuit 74 and the coupling means 73. The key preprocessing unit 211 includes a parity check circuit 6 shown in FIG.
This corresponds to a circuit in which 5 and the dividing means 67 are combined. The diffusion processing stage 212 corresponds to the one including the diffusion processing stage 76 and the parameter order changing unit 80 in FIG. However, the diffusion processing stage 76 is used N times. The diffusion processing stage 212 outputs a 32-bit parameter PP _i (i = 1, 2,..., N) in one stage of processing.

(Effect of the Invention) With such a structure, each of the diffusion processing stages of the encryption processing unit and the key processing unit is used N times by the control signal output from the diffusion processing stage number control unit to perform encryption. Processing and decryption processing are possible, and the performance (encryption speed and decryption speed) required for each use environment of the encryption device can be handled.

Example 3 This will be described with reference to FIG. This is an example in which an encryption device 13 is incorporated in an IC card 10. The encryption device 13 includes an encryption processing unit 14, a key processing unit 15, and a diffusion processing stage number control unit 16. The stage number control signal N is supplied from the data input / output device 11 to the diffusion stage number control unit 16. The key processing unit 15 includes an encryption key holding unit 12
Key and the number of diffusion processing stages
The diffusion processing stage control signal data of the key processing unit 15 input from 16 is input, and the diffusion processing stages are repeated a number of times corresponding to N, and an intermediate key is output. The encryption processing unit 14 receives the intermediate key output from the key processing unit 15, the diffusion processing stage control signal data of the encryption processing unit 14 input from the diffusion processing stage number control unit 16, and the plaintext (or ciphertext). It receives the input and repeats the diffusion process N times to output the ciphertext (or plaintext) to the data input / output device 11.

Consider the case where message authentication (data integrity) and partner authentication are performed using this IC card. In message authentication, if the message to be authenticated is large, the time required to generate an authenticator increases, so N is reduced (for example, N = 4) to improve the processing speed. In the other party authentication, N is increased to increase the encryption strength (for example, N = 8).

Fourth Embodiment In this embodiment, only the key processing unit of the first embodiment is changed to the key processing shown in FIG. 10, and portions corresponding to those in FIG. The difference from the first embodiment is that a 128-bit encryption key is input.

The input 128-bit encryption key is divided into 6 by the dividing means 67-1.
The left half of the encryption key (denoted by KL) is input to the parity check circuit 65, and the right half of the encryption key (denoted by KR) is input to the parity check circuit 65-1. The function of the parity check circuit 65-1 is the same as that of the parity check circuit 65, and checks the parity of the key every byte. KR of the key that passed the parity check circuit 65-1
Is input to the dividing means 67-2. Parity inspection circuit 65
Is input to the dividing means 67 in the same manner as in the key processing unit of the first embodiment, and the same as in the first embodiment. However,
An XOR circuit 77-2 is inserted in series with the XOR circuit 77 of each diffusion processing stage 76, and a signal is supplied to the XOR circuit 77-2 as described below. Note that the parity check circuit may be omitted in the above description, as in the first embodiment.

The KR of the key is further equally divided into a left half (represented as KR-L) and a right half (represented as KR-R) of 32 bits each by a dividing means 67-2, and is divided into signal lines 331 and 332, respectively. Supplied. KR-L and KR-R are input to the XOR circuit 77-1 and the signal line 3
KR-LKR-R is supplied on 30. KR on signal line 330
-LKR-R is input to the 1 + 3.times.i-th stage of the spreading processing stage 76, where i = 0, 1, 2,..., XOR circuit 77-2, and KR-L on the signal line 331 is subjected to the spreading process. The 2 + 3 × i-th stage of the stage 76, where i =
, 0, 1, 2,...
−R is the 3 + 3 × i-th stage of the diffusion processing stage 76, where i = 0, 1,
2 and... Are different from the first embodiment in that they are respectively input to the XOR circuits 77-2. With such a structure, the values of both the key KL and the key KR are mixed in a plurality of diffusion processing stages, that is, the 128-bit encryption key is mixed, and the key processing stage number control signal 311 According to the control, (N / 2) +4 times of control is performed, and the intermediate keys P _{0 to} P _{N + 7} are obtained.

In this way, the encryption device having the encryption key length of 128 bits, which inputs the stage number control data N as a parameter, that is, an encryption device in which the number of stages of the respective diffusion processing stages of the encryption processing unit and the key processing unit is made variable Can be realized.

Supplementary explanation of the function of the fourth embodiment using mathematical formulas The only difference from the first embodiment is the operation of the key processing unit.
A supplementary explanation is given below. Here, the function of the function _fk is the same as in the embodiment.

(Key processing) From a 128-bit encryption key, an intermediate key P _i (i = 0 to (N
+7)) is calculated.

When a parity bit is included in the encryption key, the parity bits at 8 × n, 1 ≦ n ≦ 16 at the bit position of the encryption key are checked in byte units, and the values of these parity bits are changed to zero.

The left half of the 128-bit encryption key is represented by KL, and the right half by KR. The left half of KR is represented by KR-L, and the right half of KR is represented by KR-R.

First, when r = 1 + 3 × i, i = 0,1,..., Q _r = KR−LKR−
R, when r = 2 + 3 × i, i = 0,1,..., _Qr = KR−L; When r = 3 + 3 × i, i = 0,1,..., _Qr = KR−R I do.

From the following equation, the intermediate key P _i , (i = 1,2,3,
..., 2 bytes each). Let A ₀ and B ₀ be the left and right sides of the key KL. First, let D ₀ = φ. Then, r = 1,2,3, ...,
For (N / 2) +4, P _i (i = 0 to (N + 7)) is obtained.

D _r = A _{r -1} A _r = B _{r -1} B _r = f _k (A _{r -1} , B _{r -1} D _{r -1} Q _r ) P _{2 (r -1)} = (B _r0 , B _{r1 ) P 2 (r-1)} +1 = (B r2, B r3) a r, B r, is D _r is an auxiliary variable.

[Effects of the Invention] As described above, according to the present invention, by making the number N of diffusion processing stages of the encryption processing unit variable, only one encryption device is mounted, and the optimum N is determined according to the purpose of use. , And efficient encryption processing can be performed for each application.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an encryption processing unit according to the first embodiment.
FIG. 3 is a block diagram showing a key processing unit according to the first embodiment, FIG. 3 is a block diagram showing a diffusion processing stage in the encryption processing unit, FIG. 4 is a block diagram showing a diffusion processing stage in the key processing unit, and FIG. FIG. 6 is a block diagram showing the data spreading means in the key processing unit, FIG. 7 is a block diagram showing the encryption device of the second embodiment, and FIG. 8 is a block diagram showing the second embodiment. FIG. 9 is a block diagram showing a cryptographic device of the third embodiment, FIG. 10 is a block diagram showing a key processing unit of the fourth embodiment, FIG.
FIG. 11 is a block diagram showing an encryption processing unit of a conventional encryption device,
FIG. 12 is a block diagram showing a key processing unit of a conventional encryption device.

Continuation of the front page (56) References Akihiro Shimizu, Shoji Miyaguchi, "Fast Data Enrichment Algorithm FEA L", Lecture Notes Computer, 304, (1987), p. 267- 278 Ryota Akiyama, Reigo Hachiboshi "Cryptographic Processing Hardware" Information Processing, Vol. 25, No. 6, (1984); 566-574 Shinichi Ikeno, Kenji Koyama "Modern Cryptography Theory" 3rd edition, The Institute of Electronics, Information and Communication Engineers, (May 1989), p. 56-58 D.C. Chanm, JH. Everse, "Cryptanalysis of DES with a reduced number of rounds Sequences of linear factors in blackrock Ciphers". 218, (1986), p. 192-211 (58) Fields surveyed (Int. Cl. ⁶ , DB name) H04K 1/00-3/00 H04L 9/00-9/38 G09C 1/00-5/00 JICST file (JOIS) INSPEC ( DIALOG)

Claims (2)

(57) [Claims] An encryption processing unit for receiving a plaintext or ciphertext and performing data diffusion processing with an intermediate key to output a ciphertext or plaintext, and a key for receiving an encryption key and generating the intermediate key by data diffusion processing A cryptographic processing unit comprising: a first exclusive-OR circuit that performs an exclusive-OR operation on the plaintext or ciphertext and a part of the intermediate key; and an output of the first exclusive-OR circuit. Is supplied, and a data diffusion unit in which data diffusion processing is performed by another part of the intermediate key, and an exclusive OR of an output of the data diffusion unit and the rest of the intermediate key is used to convert the ciphertext or plaintext. The data spreading section repeatedly processes the first spreading processing stage a plurality of times, and the first spreading processing stage receives the input right data as it is as the first first spreading processing stage. As left data for the diffusion stage And the data is input to the data spreading means and data is spread by a predetermined one of the intermediate keys, and the spread data and the left data are subjected to an exclusive OR operation, and the exclusive OR operation result is obtained. The key processing unit outputs the right data to the next first spreading processing stage as a right data. The key processing unit repeats the second spreading processing stage a plurality of times. The signal is output to the next second diffusion processing stage and supplied to the exclusive OR circuit. The other input of the exclusive OR circuit is the second diffusion processing stage preceding the second diffusion processing stage. Input left data is input, the output of the exclusive OR circuit is used as parameter data, the left data is spread by data spreading means, and the spread data is output as the intermediate key and A number-of-stages control data, wherein a stage number control data is set and input, and a number-of-stages control unit for outputting a number-of-stages-control signal and a key-processing-unit-number control signal is provided. Means for causing the first spreading processing stage of the encryption processing unit to repeat the process by the value N indicated by the stage number control data according to the encryption stage number control signal; and (N / 2 Means for causing the second diffusion processing stage of the key processing unit to repeat the processing by +4. 2. A cryptographic processing unit for receiving plaintext or ciphertext and performing data diffusion processing with an intermediate key to output a ciphertext or plaintext, and a key for receiving an encryption key and generating the intermediate key by data diffusion processing. A cryptographic processing unit comprising: a first exclusive-OR circuit that performs an exclusive-OR operation on the plaintext or ciphertext and a part of the intermediate key; and an output of the first exclusive-OR circuit. Is supplied, and a data diffusion unit in which data diffusion processing is performed by another part of the intermediate key, and an exclusive OR of an output of the data diffusion unit and the rest of the intermediate key is used to convert the ciphertext or plaintext. The data spreading section repeatedly processes the first spreading processing stage a plurality of times, and the first spreading processing stage receives the input right data as it is as the first first spreading processing stage. As left data for the diffusion stage And the data is input to the data spreading means and data is spread by a predetermined one of the intermediate keys, and the spread data and the left data are subjected to an exclusive OR operation, and the exclusive OR operation result is obtained. The key processing unit divides the encryption key into two parts and outputs the divided data to one of the divided parts by repeating the second diffusion processing part a plurality of times. The other half is further divided into KR-L and KR-R, and these KR-L and KR-R are subjected to an exclusive OR operation. The second diffusion processing stage performs the repetition processing a plurality of times, and outputs the right data as it is as the left data to the next second diffusion processing stage, and supplies the right data to the exclusive OR circuit. The circuit has a first stage before the second diffusion stage. The input left data of the two diffusion processing stages and the data Qr are input at the r stage (the data Qr is KR-LRK-R at r = 1 + 3 × i, r = 2 + 3 ×
i = KR-L, r = 3 + 3 × i = KR-R, i = 0,1, ...),
Using the output of the exclusive OR circuit as parameter data, the left data is spread by the data spreading means, and the spread data is output as the intermediate key and output to the next second spreading processing stage as right data. In the encryption device, a stage number control data is set and input, and a spreading stage number control unit that outputs an encryption stage number control signal and a key stage number control signal, and the encryption stage number control signal Means for causing the first spreading processing stage of the cryptographic processing unit to repeat the process by the value N indicated by the stage number control data; and the second spreading of the key processing unit by (N / 2) +4 by the key processing unit stage number control signal. Means for causing the processing stage to perform repetitive processing.