JP2658163B2 - Method of manufacturing MIS type semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an MIS semiconductor device, and more particularly, to an MIS semiconductor device having an LDD structure.

[Conventional technology]

Conventionally, this type of MIS type semiconductor device has an insulating film made of a silicon oxide film or the like as shown in FIG.
The source and the drain of the LDD structure having the low-concentration N-type diffusion layer 5 and the high-concentration N-type diffusion layer 7 were provided.

In FIG. 3, 1 is a P-type silicon substrate, 2 is a gate oxide film, 3 is a gate electrode made of polycrystalline silicon,
4 is a silicon oxide film.

[Problem to be Solved by the Invention] In the above-mentioned conventional MIS type semiconductor device having the LDD structure, since the low concentration N type diffusion layer 5 is not under the gate electrode 3, it occurs during the operation of the MIS type semiconductor device. when hot electrons are trapped in the oxide film on the 5 low concentration N-type diffusion layer, since the diffusion layer region by inverting easily not be controlled by the gate electrode 3 resistance increases, degradation of current capability g _m There was a drawback that it was easy to come.

[Means for solving the problem]

The method of manufacturing the MIS type semiconductor device comprises the steps of: forming a gate oxide film and a thin first polycrystalline silicon film for a first electrode on a first conductivity type silicon substrate; and a thick second polysilicon film for a second electrode containing a second conductivity type impurity. Forming a polycrystalline silicon film and an oxide film, and then etching the oxide film and the second polycrystalline silicon film to form a second electrode; and forming the substrate using the oxide film and the second electrode as a mask. Forming a low-concentration diffusion layer by introducing an impurity of the second conductivity type into the substrate; forming a polycrystalline silicon film for the third electrode containing the impurity of the second conductivity type on the entire surface; Anisotropically etching the polycrystalline silicon film for use and the first polycrystalline silicon film to form a third electrode on the side surface of the second electrode and a first electrode under the third electrode and the second electrode. Then, a gate electrode including the first electrode, the second electrode, and the third electrode is formed. Extent and is characterized in that a step of forming a diffusion layer of high concentration by introducing a second conductivity type impurity into the substrate using the gate electrode as a mask.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of one embodiment of the present invention. 2 (a) to 2 (c) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a manufacturing method according to one embodiment of the present invention. Hereinafter, the method will be described together with the manufacturing method.

First, as shown in FIG. 2 (a), a gate oxide film 2 having a thickness of about 200.degree. Is formed on a P-type silicon substrate 1, and a non-doped polycrystalline film which becomes a first electrode having a thickness of about 500.degree. The silicon film 11A is formed.

Next, as shown in FIG.
Forming a polycrystalline silicon film doped with phosphorus having a thickness of about 4000 mm and a silicon oxide film 8 having a thickness of about 500 mm on A,
These are patterned to form the second electrode 12. Next,
Using the second electrode 12 and the silicon oxide film 8 as a mask, an N-type impurity is introduced by an ion implantation method to form a low-concentration N-type diffusion layer 5.

Further, as shown in FIG. 2 (c), after forming a polycrystalline silicon film 13A doped with phosphorus with a thickness of about 2000 ° on the entire surface,
Annealing diffuses phosphorus throughout the polycrystalline silicon film 11A.

Finally, as shown in FIG. 1, the polycrystalline silicon films 13A and 11A doped with phosphorus are anisotropically etched to form a second electrode 12A.
The polycrystalline silicon 13A is left only on the side wall of the first electrode 1
First and third electrodes 13 are formed. Thereafter, an N-type impurity is introduced by ion implantation to form a high-concentration N-type diffusion layer 7.

According to the present embodiment thus configured, the low-concentration N-type diffusion layer 5 forms the first and third electrodes 1 forming the gate electrode 3A.
Since it exists below 1,13, the low concentration N-type diffusion layer 5 can be controlled by the gate electrode 3A.

In the above embodiment, the case where the silicon oxide film is used as the insulating film on the second electrode 12 has been described, but a high melting point metal film such as W or Mo may be used instead of the silicon oxide film. In this case, there is an advantage that the wiring resistance of the gate electrode can be reduced by about one digit.

〔The invention's effect〕

As described above, in the book, the side wall in the LDD structure is formed of polycrystalline silicon constituting the gate electrode, so that the low concentration impurity diffusion layer exists under the gate electrode and is controlled by the gate electrode. there is an effect that can prevent degradation of current capability were problem is with MIS type semiconductor device having an LDD structure g _m.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of one embodiment of the present invention, and FIGS. 2 (a) to 2 (c) are cross-sectional views of a semiconductor chip for explaining a manufacturing method of one embodiment of the present invention. Fig. 3 shows the conventional MIS
FIG. 4 is a cross-sectional view of an example of a semiconductor device. 1 ... P-type silicon substrate, 2 ... Gate oxide film, 3,3A ...
... Gate electrode, 4 ... Silicon oxide film, 5 ... Low concentration N
Type diffusion layer, 6 side wall, 7 high concentration N type diffusion layer, 8 silicon oxide film, 11 first electrode, 11A
... Polycrystalline silicon film, 12... Second electrode, 13... Third electrode, 13A... Polycrystalline silicon film.

Claims (1)

(57) [Claims] A first polycrystalline silicon film for a gate oxide film, a first electrode for a first electrode, and a second polycrystalline silicon for a second electrode containing an impurity of a second conductivity type on a silicon substrate of the first conductivity type; Forming a film and an oxide film, and then etching the oxide film and the second polycrystalline silicon film to form a second electrode;
Using the oxide film and the second electrode as a mask, a second
A step of forming a low-concentration diffusion layer by introducing impurities of a conductivity type, a step of forming a polycrystalline silicon film for a third electrode containing impurities of the second conductivity type on the entire surface and heat-treating the same, Anisotropically etching the crystalline silicon film and the first polycrystalline silicon film to form a third electrode on a side surface of the second electrode and a first electrode below the third electrode and the second electrode; Forming a gate electrode including one electrode, a second electrode, and a third electrode; and forming a second electrode on the substrate using the gate electrode as a mask.
Forming a high-concentration diffusion layer by introducing impurities of a conductivity type.