JP2006073930A - Method of changing magnetization state of magnetoresistive effect element using domain wall motion, magnetic memory element using the method, and solid-state magnetic memory - Google Patents

Abstract

A magnetic solid-state memory capable of high access and capable of long-term data storage is provided.
A magnetic memory element having a first magnetic layer, an intermediate layer, and a second magnetic layer, and recording information in the magnetization directions of the first magnetic layer and the second magnetic layer. In addition, magnetic domains that are antiparallel to each other and domain walls that separate the magnetic domains are constantly formed in at least one of the magnetic layers, and the positions of adjacent magnetic domains are controlled by moving the domain walls within the magnetic layer. Thus, a magnetic memory element that records information.
[Selection] Figure 1

Description

  The present invention relates to a non-volatile solid-state magnetic memory (MRAM) using a magnetoresistive effect element and an information recording method thereof, and more particularly, to a magnetic film having a magnetization easy axis in a direction perpendicular to a film surface as a magnetic film. The present invention relates to a resistance element and a solid-state magnetic memory using the magnetoresistance element.

  The magnetoresistive effect is a phenomenon in which the electrical resistance is changed by applying a magnetic field to a magnetic material, and is used for a magnetic field sensor, a magnetic head, and the like. For example, a magnetoresistive element using a ferromagnetic material is characterized by excellent temperature stability and a wide range of use.

  In the giant magnetoresistance effect, a laminated film in which magnetic layers and nonmagnetic layers are alternately laminated with a period of several nanometers, and the magnetic moments of the opposing magnetic layers are magnetically coupled in an antiparallel state via the nonmagnetic layers Attention has been focused on exchange coupling films formed of so-called artificial lattice films. For example, an artificial lattice film of Fe / Cr and an artificial lattice film of Co / Cu have been found.

  On the other hand, in a metal sandwich film composed of a ferromagnetic layer / nonmagnetic layer / ferromagnetic layer in which a ferromagnetic layer is laminated via a nonmagnetic metal layer, the nonmagnetic metal layer has a degree of elimination of exchange coupling between the ferromagnetic layers. The magnetic moment of the ferromagnetic layer is fixed by increasing the film thickness and placing an antiferromagnetic layer such as FeMn in contact with one of the ferromagnetic layers to exchange-couple, and only the spin of the other ferromagnetic layer A so-called spin valve film is known which can be easily switched by an external magnetic field.

Since the spin valve film has no exchange coupling between the two ferromagnetic layers, the spin can be switched with a small magnetic field, so that a magnetoresistive effect element having higher sensitivity than the exchange coupling film can be provided, and a read head for high-density magnetic recording As it is currently in practical use. Further, it has been developed as a memory element of MRAM. (Patent Document 1)
The above is the magnetoresistive effect when a current is passed through the film surface. However, it is also known that a larger magnetoresistive effect can be obtained by using a so-called perpendicular magnetoresistive effect in which a current is passed in the direction perpendicular to the film surface. ing. (Patent Document 2)
Furthermore, in a three-layer film consisting of a ferromagnetic layer / insulator layer / ferromagnetic layer, the spin current of the two ferromagnetic layers is made parallel or antiparallel to each other by an external magnetic field, so that the tunnel current in the direction perpendicular to the film surface is reduced. A giant magnetoresistive effect (TMR) by a ferromagnetic tunnel junction utilizing the fact that the sizes are different from each other is also known.

Recently, the use of giant magnetoresistive elements and ferromagnetic tunnel effect elements as magnetic memory elements has also been studied. When these elements are used in a magnetic memory device, these elements are arranged in a matrix, and a magnetic field is applied by passing a current through a separately provided wiring, so that the two magnetic layers constituting each element are parallel to each other. Alternatively, “1” and “0” are recorded by controlling in antiparallel. Reading is performed using the GMR effect or the TMR effect. (Patent Document 3)
Moreover, the domain wall motion phenomenon by the current pulse has been reported, and this is considered as follows. When a current pulse is passed through the magnetic material, spin-polarized electrons are generated due to the influence of magnetic domains in the magnetic material. When the spin-polarized electrons are injected into the magnetic material, an effect of accumulating electron spin and an effect of moving electron spin are produced. Due to these two effects, the electron spin in the magnetic material spin-injected is spin-polarized. When this polarized spin is moved to the domain wall, an internal magnetic field is generated at the domain wall. It is considered that domain wall motion is induced by the effect of the internal magnetic field. (Non-Patent Document 1)
Japanese Patent Laid-Open No. 09-095151 JP 2000-228002 A JP 2001-237472 A National Institute of Advanced Industrial Science and Technology (June 3-6/4, 2003) "New trends in spintronics" p20

  However, in the conventional magnetic memory device, the demagnetizing field in the in-film direction increases when the element size is reduced for high density recording. Therefore, in order to overcome the demagnetizing field and stabilize the recording state, it is necessary to increase the in-plane magnetic anisotropy of the recording layer. In this case, the current magnetic field required for recording becomes large, and it becomes necessary to flow a large current through the wiring. As a result, there is a problem that, in addition to requiring a power source with high power, the current density increases, electromigration occurs, and the wiring breaks. Such a tendency of increasing the current density increases in principle as the element size decreases. As described above, it is inevitable that the limit of miniaturization occurs in the method of selectively recording only by the induction of the current magnetic field.

  The present invention is a magnetization reversal method different from the conventional method, and an object thereof is to provide a magnetoresistive effect element that realizes this magnetization reversal method. The magnetic memory device using this magnetoresistive effect element reduces the power required for information recording and further provides an information recording method independent of the element size.

  In order to solve the above-described problems, the magnetic memory element of the present invention has an intermediate layer interface at the intermediate layer interface of the second magnetic layer of the magnetoresistive effect element portion having the first magnetic layer and the second magnetic layer. This magnetic domain has a configuration having a portion having a magnetization direction parallel or antiparallel to the other magnetic layer.

  In the solid-state magnetic memory of the present invention, the domain wall region of the magnetic memory element is moved by current or thermal interaction so that the magnetization of the interface between the first magnetic layer and the second magnetic layer is intermediate. The memory function is produced by controlling the parallel and anti-parallel states of the direction of the.

still,
In the ferromagnetic tunnel magnetoresistive element, the spin polarization degree of the magnetic substance at the interface of the intermediate layer is large and contributes to the magnetoresistance effect. Therefore, the magnetization state near the interface of the intermediate layer is the most in the magnetoresistive ratio that is the read signal of the memory. A big influence.

  That is, in the magnetoresistive effect element according to the present invention, due to the movement of the domain wall, the magnetic domain in the magnetic layer region that is in contact with the interface of the intermediate layer moves, and is parallel to the magnetization direction of the first magnetic layer that is the fixed magnetization layer. An antiparallel state is formed so that information can be recorded.

  In addition, a solid magnetic memory in which a plurality of memory elements are integrated can be formed by forming the magnetic layer region in which the domain wall is formed as a magnetic thin wire. A bit line and a magnetic thin line are arranged on a semiconductor substrate so as to intersect with each other, and a magnetic layer serving as an intermediate layer and a fixed magnetization layer is formed at the intersection to form a memory element. Information on the element can be selectively recorded by simultaneously applying to the element both a current pulse flowing through the magnetic wall in the magnetic thin line and a magnetic field induced from the current flowing in the bit line.

  Furthermore, the method of moving the domain wall in the magnetic layer is not only the pulse current or the combination of the pulse current and the current magnetic field described in Non-Patent Document 1, but also induces the domain wall movement phenomenon thermally using a heater element or the like. It is also possible to make it.

  The present invention provides an unprecedented new method for writing data at high speed. As a result, it is possible to provide a magnetic solid-state memory capable of high-speed access and capable of storing long-term data.

  Since information can be written with little use of a current-induced magnetic field, there is an effect of reducing an increase in current consumption due to miniaturization, and a solid-state magnetic memory with low power consumption can be provided.

  The magnetic memory element of the present invention has a domain wall in a magnetic film having a function of recording information (in a situation where at least information recording / reproduction can be performed) and moves the domain wall. Thus, information is recorded by making the magnetization direction component in the recording layer of each recording unit (bit) dominant in either the right or left (or upper or lower).

  Therefore, the magnetization of the recording layer is basically not reversed, and the area is controlled by the movement of the domain wall.

  In a solid-state magnetic memory using such a magnetic memory element, one bit of the memory element is composed of at least a magnetic film composed of domain walls and magnetic domains, and the memory elements are arranged in a matrix. Further, since the magnetic layer constituting the memory element also serves as the write line of the current magnetic field induction type memory, the wiring can be reduced, the structure of the memory becomes simple, and the peripheral circuit becomes simple.

  Since the movement of the domain wall is related to the flatness of the magnetic layer, even if the element is miniaturized, the pulse current value for moving the domain wall or the heating temperature does not increase, and the write current density is increased by the miniaturization. There is no invitation.

  The solid-state magnetic memory according to the present invention includes a selection unit that connects the above-described magnetic memory elements to a plurality of bit lines and selects at least one or more magnetic memory elements from the plurality of magnetic memory elements. It has means for applying at least a pulse current and / or heat to the second magnetic layer of the magnetic memory element, and information can be selectively recorded on the second magnetic layer by the pulse current and / or heat.

  Hereinafter, the present invention will be described in detail based on specific examples.

<First embodiment>
First, an embodiment of a memory according to the present invention will be described with reference to the drawings. FIG. 1 is a diagram for explaining the concept of the solid-state magnetic memory of this embodiment, and FIG. 2 is a perspective view of the magnetic memory element region of FIG.

  In the first embodiment, the solid-state magnetic memory shown in FIG. 1 has at least a first magnetic layer 1 and an intermediate layer 2, which are fixed magnetic layers, a second magnetic layer 3 having a domain wall and a magnetic domain, and selection at the time of reading an element. It includes a plug electrode 4 joined to the transistor 8, a wiring 5 formed mainly of a magnetic layer 3 in which a domain wall and a magnetic domain are formed, a bit line 6, and a data line 7 for controlling driving of the selection transistor. .

  The solid magnetic memory is narrower than the magnetic layer 3 on the magnetic layer 3 of the wiring 5 formed mainly of the magnetic layer 3 in which the domain wall and the magnetic domain are formed, and both ends connected to the wiring 5 of the magnetic layer 3 are exposed. Thus, the plug electrode formed on the surface of the intermediate layer 2 formed on the magnetic layer 3 and on the surface of the upper magnetic layer 1 and the magnetic layer 3 facing the surface on which the intermediate layer is formed, facing the intermediate layer 2. 4. Further, the upper magnetic layer 1 is connected to the bit line 6, the plug electrode 4 is connected to one end of the electrode of the element read selection transistor 8, and the gate electrode of the element read selection transistor 8 is connected to the data line 7.

  FIG. 2 is an enlarged perspective view of the memory element region 12 of FIG. 1. In the first embodiment, the magnetic layer 3 having a domain wall and a magnetic domain has a magnetic domain region 10 and a magnetic domain in which the directions of magnetization are aligned in parallel or antiparallel. It is comprised by the domain wall area | region 9 which separates.

  As shown in FIG. 2, the magnetic memory element formed in the memory element region 12 is formed on the magnetic layer 3 of the wiring 5 formed mainly by the magnetic layer 3 in which the domain wall and the magnetic domain are formed. Also, the intermediate layer 2 formed on the magnetic layer 3 so that both ends connected to the wiring 5 of the magnetic layer 3 are exposed, and the surface of the upper magnetic layer 1 and the magnetic layer 3 on which the intermediate layer is formed are opposed to each other. The magnetic layer 3 has a domain wall region 9 that separates the magnetic domain from a magnetic domain region 10 having a parallel or anti-parallel magnetization direction, and a plug electrode 4 formed on the surface to be opposed to the intermediate layer 2. Has been. In this embodiment, the upper magnetic layer 1 is in contact with the bit line 6 on the surface facing the intermediate layer 2, but the bit line 6 and the upper magnetic layer 1 may be connected via a connection plug. It goes without saying that it is good.

  FIG. 3 is a top conceptual view for explaining the configuration of a 5 × 5 bit solid magnetic memory in which magnetic memory elements are arranged in a matrix.

  As shown in FIG. 3, the solid-state magnetic memory of this embodiment is formed at both ends of a memory element region 12 including a magnetic memory element formed between a write line 5 and a bit line 6 orthogonal to each other and the write line. A magnetic domain 10 is formed in the write line 5 including the selected write line selection transistor 11.

  A pulse current is applied to the write line 5 from a power source (not shown) by turning on the write line selection transistor 11 which is a switch element for causing a pulse current to flow through the selected write line 5. Although not shown, a bit line selection transistor, which is a switching element for selecting a bit line, is formed at both ends of the bit line 6, and when the bit line 6 is selected, the bit line selection transistor is turned on to supply current to the bit line. Is applied.

  In FIG. 3, the entire write line 5 is formed of the magnetic layer 3 having domain walls and magnetic domains. However, it goes without saying that the magnetic layer 3 can be formed only in the memory element region 12 and the magnetic layer 3 can be connected by wiring. Nor.

  FIG. 4 is a diagram showing a recording state of the magnetic memory element of FIG.

  When the magnetization direction 13 of the upper magnetic layer 1 which is a fixed magnetization layer of the magnetic memory element and the magnetization direction 10 of the magnetic domain region of the magnetic layer 3 are parallel (FIG. 4A), the state is “0”. The antiparallel case (FIG. 4B) is set to “1”.

  In the present embodiment, the magnetic film forming the upper magnetic layer 1 and the magnetic layer 3 has anisotropy in the direction perpendicular to the film surface, and further in the magnetic layer 3 serving as a memory region having an information recording function, Domain walls and magnetic domains are formed. When there is no externally applied magnetic field, the magnetization direction 13 of the first magnetic layer and the magnetic domain region 10 in which the magnetization directions are aligned are in a stationary state, and therefore FIG. 4A or FIG. It will be in the state shown in.

  In the case of “0” in FIG. 4A, the magnetization directions of the upper magnetic layer 1 and the magnetic layer 3 (first and second magnetic layers) are parallel and the resistance is low, and in the case of “1” in FIG. The magnetization directions of the upper magnetic layer 1 and the magnetic layer 3 (first and second magnetic layers) are antiparallel and have high resistance. Since one element of the magnetic memory element of this embodiment has the two states shown in FIGS. 4A and 4B, one element can record 1 bit. In FIG. 4, the magnetic layer 3 (second magnetic layer) has all the magnetic domains facing upward or downward, but at least half of the magnetic domain 3 in the region in contact with the intermediate layer 2 is present. It is only necessary to have a magnetization direction corresponding to the information.

  Next, the recording operation of the magnetic memory element will be described with reference to FIG.

  FIG. 5 illustrates a case where the initial state changes from the state “1” shown in FIG. 4B to the state “0”.

The initial state is a state desired to be shown in FIG. The operation of reversing the magnetization of the magnetic layer 3 in contact with the intermediate layer 2 by applying the auxiliary recording current 15 to the bit line 16 and the recording current 14 to the write line 5 in the magnetic layer 3 in the state of FIG. . As shown in FIG. 5, a recording current 14 of 10 MHz to 100 MHz, 1 × 10 ⁻³ to 1 × 10 ⁻¹ mA is applied upward to the magnetic layer 3 having a domain wall and a magnetic domain in the write line 5 of the magnetic memory element. When it is made to flow in the direction, the domain wall movement occurs. The current value is set to 8 × 10 ⁻⁴ to 8 × 10 ⁻² mA, which is slightly lower than the current value at which the domain wall motion occurs, and at the same time, the auxiliary recording current 14 that assists the recording of information on the bit line 6. 1 × 10 ⁻⁴ to 1 × 10 ⁻³ mA is applied to the magnetic layer 3 having a domain wall and a magnetic domain in the write line 5 in a direction in which an upward magnetic field is generated, and a weak current-induced magnetic field is applied to the memory element. Only the domain wall of the selected memory element moves. As a result, the magnetic domain in the magnetic layer having the domain wall and the magnetic domain that was in contact with the interface of the intermediate layer in the initial state of the selected memory element moves, and the magnetic domain having different magnetization directions shown in FIG. It will be in contact with the interface of the intermediate layer.

  The directions of the recording current 14 and the auxiliary recording current 15 flow in opposite directions when the recording state is changed from “1” to “0” and when “0” is changed to “1”. Domain wall movement occurs in the direction in which the current flows. In the figure, a case where bit “1” is set to “0” is shown.

  During the recording operation, the bit line 6 to which the selected memory element is connected and the selection transistor 11 and the bit line connected to the write line 5 including the magnetic layer 3 in which magnetic domains and domain walls are formed are turned on / off. A selection transistor (not shown) for controlling is turned on.

  This recording process is an overwriting recording without an erasing process.

  In order to simplify the explanation, the auxiliary recording current 15 applied to the memory element 12 in the recording process is described as applying a direct current, but it goes without saying that a pulse current can be used. When a pulse current is used as the auxiliary recording current 15, a timing chart of the recording current 14 at the point A in FIG. 5A and the auxiliary recording current 15 at the point B in FIG. 5A is shown in FIG. Show. In FIG. 5B, the auxiliary recording current reaches the point B first. However, it is sufficient that the auxiliary recording current 15 is applied at the timing when the domain wall is moved by the recording current 14. It may be the timing when the point A is reached. Considering the movement of the domain wall, it is sufficient that the pulses of the recording current and the auxiliary recording current overlap by 1 ns or more, but it is preferable to apply them at the same timing.

  Further, even if the auxiliary recording current 15 is not supplied to the bit line 6, recording can be performed only with the recording current. However, when one memory is selected from the memory elements arranged in a matrix, it is preferable to use a recording current and a bit line together. However, the current value of the auxiliary recording current 15 flowing through the bit line is read out. The current value may be approximately the same as the current value at the time, and the current consumption can be significantly reduced as compared with the case where information recording is performed only by induction of the current magnetic field.

  Next, a method for reading the recorded state recorded in the magnetic memory element will be described.

  FIG. 6 is a circuit diagram showing the concept of the circuit configuration of the magnetic memory for explaining the reading process.

  FIG. 6A is a diagram showing a magnetic memory element configuration and a symbol corresponding thereto, and FIG. 6B is a circuit diagram of a 2 × 2 bit solid magnetic memory.

  The magnetic memory element includes a plug electrode 4 formed opposite to a magnetic thin film 3 having a domain wall and a magnetic domain, an intermediate layer 2 and an upper magnetic layer 1, and an upper terminal 30 is formed on the upper magnetic layer. A first terminal and a second terminal are formed on the magnetic thin film 3 having magnetic domains, and a plug terminal 33 is formed on the plug electrode 4.

  FIG. 6B is a circuit diagram of a solid-state magnetic memory having a unit cell of 2 × 2 bits. A bit line selection transistor 19 formed at both ends of the bit line 6 and the bit line 6, a write line 5, and both ends of the write line 5 are shown in FIG. A read element in which a gate is connected to the write line selection transistor 11, the read element selection line 26, and the read element selection line 26, one end is connected to the plug terminal 33 of the magnetic memory element, and the other end is connected to the word line 18. It consists of a selection transistor and a memory element. The memory element is connected in series to the write line selection transistors formed at both ends of the write line 5 via the first terminal 32 and the second terminal book 33.

  The bit line selection transistor 19 is connected to a bit line selection circuit (not shown) through a gate, and one end is connected to the write line 5. The other end of the bit line selection transistor 19 is connected to the bit line 6 of another adjacent unit cell (not shown).

  The write line selection transistor 11 is connected to a write line selection circuit (not shown) through a gate, and one end is connected to the write line 5. The other end of the write line selection transistor 11 is connected to a write line 5 of another adjacent unit cell (not shown).

  The method for reading the recorded state recorded in the magnetic memory element is as follows: the bit line selection transistor 19 at both ends of the bit line to which the selected magnetic element is connected and the read element selection transistor 11 connected to the selected magnetic memory element. Are turned on and all other selection transistors are turned off.

  As a result, a current flows between the upper terminal 30 and the plug terminal 33 of the selected magnetic memory element. If the magnetization of the upper magnetic layer 1 of the memory element and the magnetic thin film 3 having a domain wall and a magnetic domain facing the upper magnetic layer 1 are parallel, the tunnel current is small, and if the magnetization is antiparallel, the magnetic field is large. Since the resistance effect is shown, the recording state of the memory element selected to be read can be read. Actually, it is possible to determine “0” or “1” by comparing the resistance value of the reference element with a sense amplifier (not shown) connected to the bit line.

The solid-state magnetic memory of this embodiment is manufactured by applying a normal CMOS process if the switching element is a silicon substrate, and applying a high-temperature polysilicon process or a low-temperature polysilicon process if the substrate is a glass substrate. The magnetic thin film of the magnetic memory element is formed by sputtering a thin magnetic film of rare earth metal, transition metal alloy or the like with a thickness of 10 to 500 nm, and the intermediate layer is an insulating film such as Al ₂ O ₃ Can be manufactured by forming a film of approximately 0.5 nm to 5 nm and subjecting it to an oxidation treatment.

The dimensions of the upper magnetic layer (TbFe) and the intermediate layer (Al ₂ O ₃ ) are 0.1 × 0.1 μm, the plug electrode is an aluminum alloy, the dimensions are 0.1 × 0.1 μm, the thickness is 200 nm The magnetic thin film 3 (GdFe) having a domain wall and a magnetic domain has a size of 0.1 × 20 μm, and wirings such as bit lines and word lines are made of an aluminum alloy with a width of 0.1 μm and a thickness of 1 μm.

In this embodiment, a magnetic film formed by sputtering an alloy film of a rare earth metal and a transition metal is used. However, as a function of this magnetic film, it is necessary to be able to form a domain wall and a magnetic domain. Any material may be used as long as it satisfies the magnetic film. Further, although an Al ₂ O ₃ film is used as the intermediate layer, any insulating film may be used as long as a tunnel effect needs to be generated as a function of the insulating film and the insulating film satisfies the tunnel effect.

  Therefore, in the present invention, a rare earth metal such as Tb, Gd, and Dy and a magnetic thin film such as Fe, Co, and Mn are formed by sputtering to form a film having a thickness of, for example, about 10 nm to 1 μm, or vapor deposition. The magnetic film can be used as a magnetic film that satisfies the above conditions by, for example, inducing magnetic anisotropy. As the film forming method, any of a physical vapor deposition method such as sputtering and a chemical vapor deposition method such as CVD can be used.

  In the above description, the configuration of the memory cell is described using an example in which the configuration is 5 × 5 bits or 2 × 2 bits. However, the bit configuration is completely arbitrary, and the number of bits should be a megabit or gigabit level. preferable.

In addition, the operation of the sense amplifier, which is a circuit for generating a comparison voltage, can be performed by a voltage generated from a comparison memory element or the like, and the same effect can be obtained by other methods such as using a voltage between resistors. be able to.
<Example 2>
The second embodiment realizes a solid-state magnetic memory that moves a domain wall by forming a thermal gradient.

  Although Example 1 showed about the example which produces a domain wall movement by a pulse current and a current induced magnetic field, this Example implement | achieves the memory by the domain wall movement by the thermal gradient from a heater element.

  The configuration of the magnetic memory element of this embodiment is such that a heater is provided so as to face each other with the plug electrode of the magnetic memory element described with reference to FIG.

  A schematic configuration of the magnetic memory element of this embodiment will be described with reference to FIG.

  A laminated film of the intermediate layer 2 and the upper magnetic layer 1 is formed on the magnetic thin film 3 having a domain wall and a magnetic domain, and a surface facing the surface on which the laminated layer of the magnetic thin film 3 having a domain wall and a magnetic domain is formed. A plug electrode 4 is formed on the surface. Two heater elements 20 for controlling the domain wall movement are formed on the surface of the magnetic thin film 3 having the domain wall and the magnetic domain 3 on which the plug electrode 4 is formed. The heater element 20 is formed on the magnetic thin film 3 having a domain wall and a magnetic domain via an insulating film (not shown). The solid-state magnetic memory has at least a bit line 6 connected to the upper magnetic layer of the magnetic memory element. The heater element 20 has one end connected to the heater element 20 and a gate terminal connected to the heater element selection line 22. A heater element selection transistor having the other end connected to the power supply circuit is provided. As the heater material, a metal nitride silicide such as TaSiN is preferable because of its high thermal efficiency.

  By causing a current to flow through one of the two heater elements 20 to partially raise the temperature of the magnetic thin wire, a magnetic gradient is induced in the magnetic thin film 3 having domain walls and magnetic domains, thereby inducing domain wall movement. Then, information recording is performed.

  The magnetic film that induces the domain wall movement has a domain wall coercive force that is higher than that of a Tb-based material in order to perform domain wall movement with a Tb-based material having a high domain wall coercive force so that the domain wall does not move and an antiferromagnetic layer that causes exchange coupling. It has a three-layer structure with a low Gd-based material. In the region where the temperature from the heater is equal to or lower than the Curie temperature Tc of the Tb material, the domain wall of the Tb material is transferred to the Gd material. Since these three layers are exchange coupled, the domain wall cannot move. When the temperature from the heater reaches Tc, the exchange coupling between the three layers is broken. In the magnetic layer that moves the domain wall, a temperature gradient is generated by heating the heater, and the magnetic wall energy of the Gd-based material moves to the higher temperature side because the domain wall energy is lower at higher temperatures. Thereafter, when the heater is turned off and the temperature falls below Tc, the domain wall is fixed by exchange coupling. In the case of rewriting information, the information can be rewritten by heating and cooling the heater on the opposite side in the same manner.

  In addition, the temperature gradient by heater heating should just have the maximum temperature just above a heater, and can raise temperature to the grade which does not exceed Tc of an adjacent element.

  The write operation will be described below.

  The heater element selection transistor 21 is a transistor for energizing and interrupting the heater element 20 and is controlled to be turned on / off by a heater element selection line 22 signal. The second magnetic layer 3 is in contact with the first magnetic layer 1 via the intermediate layer interface, and is thermally coupled to the heater element 20.

  The heater element 20 is energized by the signal (voltage) of the heater element selection line 22 connected to the gate terminal of the heater element selection transistor 21, and the magnetic thin film 3 having a domain wall and a magnetic domain is partially heated.

  As an initial state, the second magnetic layer 3 is composed of magnetic domains that are uniformly magnetized in the direction perpendicular to the film surface. Information “0” and “1” are recorded in the memory cell area shown in FIG. As described with reference to FIG. 4, the recording state is that the magnetization direction of the first magnetic layer 1 is parallel to the magnetization direction of the magnetic domain portion in contact with the intermediate layer interface in the second magnetic layer 3. In this embodiment, the parallel state is set to “0” and the anti-parallel state is set to “1”. When writing data, a signal is input to any one of the heater element selection lines 22, and one heater element selection transistor 21 is turned on. As a result, the heater element 20 connected to the heater element selection transistor is heated, and the temperature of a part of the second magnetic layer 3 thermally coupled to the heated heater element 20 is increased and heated. The magnetic domain region on the interface of the intermediate layer 2 can be moved by moving the domain wall near the second magnetic layer 3 to a high temperature region where the energy of the domain wall is small. Specifically, the heater element is raised to 200 to 600 ° C. to provide a temperature gradient shown in FIG.

  When magnetizing in the direction opposite to that described above, recording can be performed by selecting the reverse heater element.

  This recording process is an overwriting recording without an erasing process.

  The dimensions and materials of the magnetic memory element and wiring are the same as those in the first embodiment.

  Next, a reading method will be described. FIG. 8 shows a reproduction process when a read current is supplied to the word line 24 of the memory element in the recording state shown in FIG.

  FIG. 8 is a circuit diagram showing the concept of the circuit configuration of the solid-state magnetic memory for explaining the reading process.

  FIG. 8A is a diagram showing a magnetic memory element configuration and symbols corresponding thereto, and FIG. 8B is a circuit diagram of a 2 × 2 bit solid magnetic memory.

  The magnetic memory element includes a plug electrode 4 formed opposite to a magnetic thin film 3 having a domain wall and a magnetic domain, an intermediate layer 2 and an upper magnetic layer 1, and an upper terminal 30 is formed on the upper magnetic layer. A first terminal and a second terminal are formed on the magnetic thin film 3 having magnetic domains, and a plug terminal 33 is formed on the plug electrode 4.

  FIG. 8B is a circuit diagram of a solid-state magnetic memory having a unit cell of 2 × 2 bits. A read element in which a gate is connected to the write line selection transistor 11, the read element selection line 26, and the read element selection line 26, one end is connected to the plug terminal 33 of the magnetic memory element, and the other end is connected to the word line 18. It consists of a selection transistor 17 and a memory element.

  Two memory elements are connected in series via the first terminal 31 and the second terminal 32 between the write line selection transistors formed at both ends of the write line 5, and further on the lower surface of the memory element. The heater element 1 is formed. Note that the heater element selection transistor and the heater element selection line connected to the heater element described in FIG. 7 are omitted.

  The bit line selection transistor 19 is connected to a bit line selection circuit (not shown) through a gate, and one end is connected to the write line 5. The other end of the bit line selection transistor 19 is connected to the bit line 6 of another adjacent unit cell (not shown).

  The write line selection transistor 11 is connected to a write line selection circuit (not shown) through a gate, and one end is connected to the write line 5. The other end of the write line selection transistor 11 is connected to a write line 5 of another adjacent unit cell (not shown).

  At this time, a current flows through an intermediate layer of the selected magnetic memory element by activating the bit line 19 and the read element selection line 26 to which the selected magnetic memory element is connected. If the direction of magnetization of the magnetic domain regions on the upper and lower sides of the intermediate layer interface is parallel, the tunnel current is small, and if it is antiparallel, the magnetoresistive effect is increased. Can do.

  Actually, the resistance value of the reference element is compared with a sense amplifier (not shown) connected to the bit line to determine “0” or “1”.

The figure which shows the structure of one Example of the memory element in the memory of this invention. 1 is a perspective view of a memory element in Embodiment 1. FIG. FIG. 3 is a diagram illustrating a configuration of a multi-bit memory in which the memory elements according to the first embodiment are arranged in a matrix. The figure which shows the recording state of this invention. The figure which shows the recording process of this invention. The figure which shows the reproduction | regeneration process of the memory element of this invention. The figure which shows the recording process of Example 2 of the memory element of this invention. The figure which shows the reproduction | regeneration process of Example 2 of the memory element of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Upper magnetic layer 2 Intermediate | middle layer 3 Magnetic layer which has a magnetic wall and a magnetic domain 4 Plug electrode 5 Write line 6 Bit line 7 Data line 8 Element read selection transistor 9 Domain wall 10 Magnetic domain area | region where the direction of magnetization aligned 11 Write line selection transistor 12 Memory Element area 13 Direction of magnetization of upper magnetic layer 14 Recording current 15 Auxiliary recording current 16 Direction of magnetization in magnetic domain 17 Read element selection transistor 18 Word line 19 Bit line selection transistor 20 Heater element 21 Heater element selection transistor 22 Write selection data Line 23 Element read selection transistor 24 Data line 25 Bit line selection transistor 26 Read element selection line

Claims (6)

  A magnetic memory element having a first magnetic layer, an intermediate layer, and a second magnetic layer, wherein information is recorded in the direction of magnetization of the first magnetic layer and the second magnetic layer, and at least one of them In the magnetic layer, magnetic domains that are antiparallel to each other and domain walls separating the magnetic domains are constantly formed, and by moving the domain wall in the magnetic layer, the position of adjacent magnetic domains is controlled to record information. A magnetic memory element characterized in that: A magnetic memory element in which at least a first magnetic layer, an intermediate layer, and a second magnetic layer are stacked, and information is recorded in the magnetization direction of the first magnetic layer and the second magnetic layer,
The second magnetic layer steadily forms magnetic domains that are antiparallel to each other in the magnetic layer and domain walls that separate the magnetic domains,
The magnetic memory element, wherein the second magnetic layer has a surface exposed from the intermediate layer in a direction of current flowing through the second magnetic layer.   3. The magnetic memory element according to claim 1, wherein the second magnetic layer has magnetic anisotropy in a direction perpendicular to the film surface.   4. The magnetic memory element according to claim 1, further comprising means for moving a domain wall formed in advance in the second magnetic layer by using an electric current and / or heat. 5. Solid magnetic memory.   A bit line connected to the magnetic memory element according to claim 1, wherein the second magnetic layer is provided in common to a plurality of the magnetic memory elements, A domain wall is provided in each of the magnetic memory elements, and selectively uses the current magnetic field obtained by flowing a current in the second magnetic layer and flowing a current in the bit line, thereby selectively providing information. A solid-state magnetic memory characterized by recording.   4. A heating unit disposed in the vicinity of the magnetic memory element according to claim 1, wherein the second magnetic layer is provided in common to the plurality of magnetic memory elements, and the domain wall is provided. Is provided in each of the magnetic memory elements, and selectively records information by passing a pulse current through the second magnetic layer and increasing the temperature in the vicinity of the specific magnetic memory element by the heating means. A solid-state magnetic memory characterized by that.

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