HK1001079A1

HK1001079A1 - Scanning method and device for use in particular in wireless telecommunications equipment

Info

Publication number: HK1001079A1
Application number: HK98100175A
Authority: HK
Inventors: Wedi Christoph
Original assignee: Siemens Aktiengesellschaft
Priority date: 1992-10-30
Filing date: 1993-10-12
Publication date: 1998-05-22
Also published as: DE4236775A1; FI952055A7; EP0667073B1; WO1994010777A1; DE59306414D1; AU5147893A; ES2102063T3; DE4236775C2; FI952055A0; FI952055L; EP0667073A1

Abstract

In the scanning method proposed, a scanning phase is generated in order to synchronize an asynchronous digital-data flow by comparing actual and reference subdata bit sequences in part of the data flow scanned at the data-bit level.

Description

The invention relates to a scanning process, in particular for wireless telecommunications equipment, as defined in the patent claim 1 and to a scanning device, in particular for wireless telecommunications equipment, as defined in the patent claim 9.

Communication systems with wireless telecommunications equipment for the wireless transmission of voice and non-voice information are bound in their technical development, analogous to the long-standing standard ISDN (Integrated Services Digital Network) in wired communication technology, to various standards. In addition to some national standards and several transnational standards, such as the CT1, CT1+ standard on an analogue basis and the CT2, CT3 standard on a digital basis, at European level, analogous to the global GSM standard (Groupe Spéciale Mobile or Globals Systems for Mobile Communication) for mobile communications, for which lower performance wireless communication between wired devices (Portable) and the connected wireless network (BECT) is based on a single 100 m broadband standard called DECT.

For wireless communication according to the DECT standard, a dynamic channel selection is carried out of approximately 120 available channels. The 120 channels result from the fact that the DECT standard uses ten frequency bands between 1.8 and 1.9 GHz, wherein in the frequency band, as shown in Figure 1, in the time multiplex (TDMA = Time Division Multiple Access) with a time multiplex frame of 10 ms is worked. In this time multiplex frame 24 (from 0 to 23) time channels are defined and thus a frame scheme is specified. This MS-scheme is then used so that for each frequency band 12 e.g. mobile BS-stations with a base of a DECT communication system can operate simultaneously in a duplex (BS - BS - or MS-station) and 24 μm of time slot (MS-BS - or MS-MS) is allocated to each of the two simultaneous time slots.

This time slot specifies the time in which information (data) is transmitted. This transmission of information in duplex operation is also called ping-pong method because it is sent at a certain time and received at another time. In this ping-pong method, a time frame or pulse (burst) of 365 μs is transmitted in each time slot, which corresponds to about a frame length of 420 bits, with a data throughput of 42 kBit/s.

Err1:Expecting ',' delimiter: line 1 column 857 (char 856)

Err1:Expecting ',' delimiter: line 1 column 630 (char 629)

In addition, the DECT standard, analogous to the ISDN standard with the ISO/OSI 7-layer model, defines further layers (layers). One of these layers is a Medium Access Control Layer (MAC-L), to which, according to Figure 3, in an A field and in a B field, the 388 bits for the transmission of utility information are allocated. The A field comprises 64 bits, which are used, among other things, for messages when connecting the base and mobile stations of the DECT communication system. The remaining 324 bits of the B field, of which 320 bits are used for voice data and 4 bits for detecting partial pulse interference, are allocated further to ISO/IOS.

The DECT communication system has in its simplest form a base station with at least one mobile station. More complex (e.g. networked) systems contain several base stations with several mobile stations each. Due to the 24 time channels defined in the DECT standard, up to 12 mobile stations can be assigned to the base station, which communicate with the base station in duplex operation.

Figure 4 shows a typical DECT wireless communication KA arrangement in which the mobile station MS is the transmitter SG and the base station BS is the receiver EG. Based on the above, the wireless KA arrangement can also be modified to make the base station BS the transmitter and the mobile station MS the receiver EG. The transmitter SG has a transmitter antenna SA, through which a radio signal generated by the transmitter SG is sent to the receiver EG. To be able to receive the radio signal, the receiver EG has a receiver EA.

The radio signal FS is a high frequency carrier signal with a carrier frequency between 1.8 and 1.9 GHz modulated by a digital data stream SDS with a transmitter-specific time (phase) in the SG transmitter, according to the DECT transmission agreement underlying the DECT communication system. The digital data stream in the SG transmitter contains the information necessary for wireless transmission. This information includes, among other things, the synchronisation and usage information already mentioned, which is contained in the DECT standard, e.g. in a 420-bit flash information packet (PH-package). This information or data package now produces the SG transmitter modulating the radio signal (FST) according to the standard frequency and time-scale for transmission, in accordance with the DMR, in the period of time provided by the SG transmitter.

In order to decrypt the transmitted information packet (transmitted voice information per time slot TS), the radio signal FS (modulated carrier signal) must be demodulated in the EC receiver. In the EC receiver, the demodulation results in a digital receiving data stream EDS which, in an uninterrupted transmission of the radio signal FS, has the same bit structure as the transmitting data stream SDS (right-receiving data stream EDS) and which, in an interrupted transmission of the radio signal, has a different bit structure from the state current (left-receiving data stream). After this demodulation of the radio signal FS and the associated generation of the receiving data stream EDS, this must be synchronized on the EC receiver for further processing in the end spectrum.

EP-A2-0 471 207 provides a circuit arrangement and a method for regenerating and synchronising a digital signal, whereby the digital signal can be easily and error-free regenerated and synchronised independently of a phase, jitter and wander to the system clock by sensing the digital signal in the centre of its eye.

EP-0 268 694 A1 provides a procedure and arrangement for synchronising signals transmitted in time-multiplex operation, whereby signals received in a substation of a transmission network are scanned in steps of the substation's own bit rate, the scan values are checked for consistency with a synchronous word transmitted in the time-multiplex frame and the temporal position of those correctly rendered synchronous response scan values is determined within the bit rate steps.

DE-36 11 959 A1 provides a synchronisation method for radio signals transmitted in burst mode, whereby for rapid synchronisation of the bit and frame phases, each bit of a preamble of the radio signal is continuously scanned n times, in which case the consecutive signal response values for a given bit phase are formed into signal response sequences with a number corresponding to the number of bits in the preamble, the signal response sequences are compared in their sequence with the preamble recorded on the receiver for consistency and the correct bit and frame phases are determined depending on the results of the comparison.

The purpose of the invention is to specify a sampling method and a sampling device, particularly for cordless telecommunications equipment, in which a sampling phase is generated from a sub-data stream of a digital asynchronous data stream to synchronize the data stream to a clock (device clock) even with a slightly distorted sub-data stream (e.g. pulse-to-break ratio of the data stream of 70/30).

This task is solved, on the basis of the test procedure defined in the general concept of claim 1 by the characteristics specified in the characteristic part of claim 1 or the test device defined in the general concept of claim 9 by the characteristics specified in the characteristic part of claim 9.

In the sampling method or device, a sampling phase for synchronising an asynchronous data stream is generated by means of a target/actual comparison of sub-data bit sequences of a data bit-sampled synchronisation-relevant sub-data stream of the data stream.

Beneficial continuing education of the invention is given in the subclaims.

An example of the invention is illustrated by the drawings in Figures 5 to 9 which show: Figure 5 shows the basic design of a wireless telecommunications device with a receiving and digital part,Figure 6 shows the basic design of the digital part in terms of demodulation of a modulated analog signal and generation of a sampling phase to synchronize a digital asynchronous data stream to a device clock,Figure 7 shows the basic design of a sampling phase generation device,Figures 8 and 9 show a comparison arrangement for performing a subbit/bit-by-bit comparison.

Figure 5 shows a block diagram of the layout of a wireless telecommunications equipment 1 as it can be used, for example, as a base station or mobile station in a wireless communication system, in particular as defined by the DECT standard. The wireless telecommunications equipment 1 is equipped with, among other things, a receiver part 10 for receiving analogue RF signals AS modulated for information transmission, a digital part 13 for evaluating and processing a digital data stream DS modulated from the respective RF signal AS and a peripheral part 18 for outputting and forwarding the information transmitted using the HF signal AS and the digital data stream DS.

The receiver part 10 of the wireless telecommunications equipment is connected to a radio interface with an antenna 11 on a radio transmission line 2 to a transmitter 3 transmitting the RF signal AS. The antenna 11 is downlinked to a receiver 12 with a receiver 120 (receiver) and a demodulator 121 (demodulator). The receiver 120 is constructed in the conventional way and prepares the modulated analogue RF signal AS received from the antenna 11 for demodulation in the demodulation circuit 121. In this demodulation of the RF signal AS 121 the output of the digital data demodulation circuit 121 is generated by the digital data demodulation circuit 121. The data stream generated by the digital data modulation is transmitted from a digital data input (DSM) of 10 to 14 Mbit/s in a direction from 1 to 14 Mbit/s at a steady digital data input of 13 to a digital data input of 13 to 1.

This high transmission rate places particular demands on the control unit 14 which controls all the procedures and processes required for the evaluation and further processing of the digital data stream DS in the digital part 13.

The controlled by the control unit 14 is affected by, inter alia, the demodulation circuit 121 which is connected to the control unit 14 directly via a first control line 5 and indirectly via a second control line 6 via a compensation circuit 19 of the receiving part 10.

The control unit 14, which, in particular, when receiving the digital data stream DS, synchronises the digital part 13 with the demodulated data stream DS and provides connections in the TDMA process, is in turn assigned to a microprocessor control unit 16 via a bus interface 15. The microprocessor control unit 16 contains a microprocessor 160 and a digital memory unit 161 which is connected to the microprocessor 160 and is responsible for all control and programming operations in the wireless telecommunications device 1. For example, the control line 14 is programmed indirectly via bus unit 15 by the microprocessor control unit 16.

In addition, an ADPCM and CODEC circuit 17 is controlled by the microprocessor controller 16. The ADPCM and CODEC circuit 17 performs an interface function between the controller 14 and the peripheral part 18 of the wireless telecommunications equipment. For this interface function, the ADPCM and CODEC circuit 17 is partially controlled by the controller 14 in addition to the microprocessor controller 16.

Figure 6 shows in a block diagram the basic structure of the control unit 14 for synchronising the digital data stream DS received from the receiving unit 10 - arranged in digital part 13 as shown in Figure 5. The control unit 14 has a scan phase generator 140 to which the digital data stream DS is fed to generate a scan phase APH. To generate this scan phase, the scan phase generator 140 is connected to an oscillator 141, a register device 142 and a noise detection circuit 143.

The oscillator 141 generates a TSI clock signal whose clock frequency is n times the frequency of the transmission rate of the digital data stream DS. The TSI clock signal is fed to the register 142 in addition to the scan phase generator 140. During the generation of the scan phase, APH status notifications SM0, SM1 are exchanged cyclically (e.g. for m = 3 cycles) between the register 142 and the scan phase generator 140. The controller 142 also receives a status notification SM2 as described in the microprocessor code 130, digital component design regulation 130, and a status notification SM2 as described in the noise-disconnection code 143. The status notifications are assigned as dynamic status notifications, for example, in the direction of the SM 143, and the status notifications are assigned to the SM 143, the controller 143, the controller 143, the controller 143, the controller 143, the controller 143, the controller 143, the controller 143, the controller 143, the controller 143, the controller 143, the controller 143, etc. The status notifications are assigned as dynamic status notifications, for example, in the direction of the SM 142, and the status notifications are assigned to the controller 143, the controller 143, the controller 143, the controller 143, the controller 143, the controller 143, the controller 143, the controller 143, the controller 143, the controller 143, the controller 143, the controller 143, the controller 143, the controller 140, controller 140, controller 140, controller 140, controller 140, controller 140, controller 140, controller 140, controller 140, controller 140, controller 140, controller 140, controller 140, controller 140, controller 140, controller 140, controller 140, controller 140, controller 140, controller 140, controller, etc.

at the time of receipt of the last status message SM1, the scan phase generator 140 generates the final scan phase from the digital data stream DS and the TSI clock signal, which is then fed in addition to the digital data stream DS to synchronize a synchronization device 144. The synchronization device 144 generates a synchronized digital data stream SY-DS from the digital data stream DS and the scan phase APH, which is then processed in the control unit 14 of the wireless telecommunications device 1. However, the APH scan phase generated by the scan phase generator 140 is fed not only to the synchronization device 144 but also to the receiver. The synchronization device is also fed in conjunction with the control control unit 142 through the control control control unit 5 of the DS-registry, in accordance with Figure 142 of the Regulation No 142 and Figure 5 of the Regulation No 142 of the DS-registry.

Figure 7 shows in a block diagram the basic structure of a phase-generation device which, according to Figure 6, consists of the phase-generator 140, the oscillator 141, the register 142 and the noise detection circuit 143. The phase-generator 140 contains a suppression circuit 1400, a register 1401 connected to the suppression circuit 1400, a bit sequence detection circuit 1403 connected to the register 1401 via a BUS interface device 1402 and a selection circuit 1404 connected to the bit sequence detection circuit 1403. The gas-generator 140 has a function to synchronize data, in particular with the data-generation device 1400, and to synchronize data from the DS-PATH (Directory of Digital Equipment) 142 and the data-transmission function of the DS-PATH (Directory of Digital Equipment) 143.

The digital data stream DS fed to the sampling phase generator 140 of the control unit 14 is first fed to the suppression circuit 1400. This suppression circuit 1400 is a circuit operating on the slide register principle, where a clock must be installed to push data streams through. In order to push the digital data stream DS through the suppression circuit 1400, the clock signal generated by the oscillator is fed to the suppression circuit 1400 with an n-clock frequency TFn by the TSI with an oscillator. The T-signal attached to the suppression circuit 1400 is then fed to the digital data stream DS. The data substrate data is then transmitted by the TSI. The data substrate data is transmitted by the T-bit rate of the TFF T-signal. The data substrate data to be transmitted in this TSI is described in more detail in this TSI as the SDB and the data substrate data to be transmitted by the SDB.

For the description and error checking of the SDBF sub-data sequence, it is advantageous to scan the individual data bit DB of the DS digital data stream as often as possible.However, since the individual data bits DB of the DS digital data stream are fed to the scan phase generator 140 and the suppression circuit 1400 at a transmission rate of 1.152 MBit/s, an n-fold scan of the DS digital data stream from the oscillator 141 in relation to the transmission rate of the DS digital data stream also needs to generate a clock frequency n times as large as possible.However, for such a digital data stream DB of the DS digital data stream, the data generator must also generate the parts of the DS digital data stream allocated to the scan phase generator 140 and the suppression circuit 1400 at a transmission rate of approximately 140 MHz.The n-fold scan is carried out between these two t-speed switches by the oscillator 1404 T-speed switches (in the case of the TF TSI 1410), which is also considered to be a real-time analogue to the data transmission rate of the TF TSI 1410 (in the case of the TF TSI 1410), which is also considered to be a real-time analogue to the data transmission rate of the DS digital data stream.

For the digital data stream DS fed to suppression circuit 1400, this means that for each data bit DB fed into suppression circuit 1400, 9 sub-data bits SDB (sampling values) are generated.

Err1:Expecting ',' delimiter: line 1 column 115 (char 114)

Err1:Expecting ',' delimiter: line 1 column 225 (char 224)

In addition, each sliding register SR1...SR4 which is placed in the register 1401, such as the transmission circuit 1400, can always intercept only one data bit DB of the data stream DS at a time.

For purposes of a later target/actual comparison, these sub-data bits SDB stored in the register 1401 are hereinafter referred to as actual sub-data bits I-SDB.

In analogy, the SDBF sub-data sequence of the real sub-data bits I-SDB stored in register base 1401 is a real sub-data sequence I-SDBF and the digital data stream DS is a real data stream I-DS. The real sub-data bit I-SDBF stored in register base 1401 changes with each stroke of the TSI clock signal attached to the slider registers SR1...SR4. For example, after 36 consecutive strokes of the clock signal interface TSI is set in the 9th interfacing cell of the SR4 register, the interfacing real sub-data bit I-B is transmitted from the 9th interfacing cell of the SR1 to the 1st interfacing cell of the SR1 to the 1402 in the direction opposite to the BUSB connection in each of the 14 bits of the SR1 and 1403 registers.

Err1:Expecting ',' delimiter: line 1 column 234 (char 233)

Err1:Expecting ',' delimiter: line 1 column 51 (char 50)

Err1:Expecting ',' delimiter: line 1 column 489 (char 488)

According to Figure 8, of the 28 Ist sub-databits I-SDB, e.g. 5 Ist sub-databits I-SDB from the SR1 slide register, 9 Ist sub-databits I-SDB from the SR2 slide register, a further 9 Ist sub-databits I-SDB from the SR3 slide register and 5 Ist sub-databits I-SDB from the SR4 slide register, these 28 Ist sub-databits I-SDB are allocated for comparison the same number of target sub-databits S-SDB to the target sub-databit S-SDBF. The target sub-databit S-SDBF is thus a transmission of S-SDB sub-signal matching that would be received from the I-SDF if the DECT communication data stream were received only via the ASF 1 without interference.

Err1:Expecting ',' delimiter: line 1 column 51 (char 50)

Err1:Expecting ',' delimiter: line 1 column 244 (char 243)

Err1:Expecting ',' delimiter: line 1 column 497 (char 496)

Err1:Expecting ',' delimiter: line 1 column 346 (char 345)

The detection signal ESI is only given when the comparator VG reports a correspondence between the sub-data bit sequences I-SDBF, S-SDBF. For example, the selection circuit 1404 is trained as a counter, clocked by the oscillator 141 and reset by the detection signal ESI at the fifth clock.

Err1:Expecting ',' delimiter: line 1 column 299 (char 298)

If the procedure described above is m times, where m is generally less than n (e.g. m = 3), the counting device 1421 waits for an additional signal ZS from the bit-same detection circuit 1420 and for the statusmel-SM3 of the noise detection circuit 143 and the status message SM2 of the microprocessor regulation 16.

This status message SM1 stops the counting function of the selection circuit 1404 and generates the APH scan phase by the last input of the ESI detection signal.

The transmission of the additional signal ZS informs the meter 1421 from the bit-parity detection circuit 1420 that the sync initiation word SY-EW has ended and the sync confirmation word SY-BW has begun, indicating that the APH scan phase for synchronization must be generated by that time.

Err1:Expecting ',' delimiter: line 1 column 124 (char 123)

The status message SM2 shall inform the meter 1421 whether a DECT-specific time slot TS is present.

The APH scanning phase generation procedure described in Figure 8 above applies with one exception to the case shown in Figure 9, where the generation procedure is performed only if the following bit combinations occur: Other

b1	b8	b9
0	0	0
0	1	0
1	1	0
1	1	1

The other bit combinations . Other

b1	b8	b9
0	0	1
1	0	1

and Other

b1	b8	b9
1	0	0
0	1	1

are either suppressed by the suppression circuit 1400 or not synchronized because there is no data bit mean.

Claims

Sampling method, in which
(a) a data stream component (SY-EW), which is relevant to synchronization, of a digital data stream (DS) in the form of n-fold sampling of each data bit (DB) is sampled and, in the process, subdata bits (SDB) are respectively generated,

(b) sampled actual subdata bits (I-SDB) of actual data bits (I-DB) of an actual data stream component (I-DS) are buffered as an actual subdata bit sequence (I-SDBF),

(c) the actual subdata bit sequence (I-SDBF) is changed with each sampling by storing a new actual subdata bit (I-SDB) and deleting the actual subdata bit (I-SDB) which has been buffered the longest,

(d) the respectively buffered actual subdata bit sequence (I-SDBF) is compared with a reference subdata bit sequence (S-SDBF) of reference subdata bits (S-SDB) which are assigned to at least two successive reference data bits (S-DB) of a reference data stream component (S-DS),

(e) a sampling phase (APH) is determined if the actual subdata bit sequence (I-SDBF) corresponds to the reference subdata bit sequence (S-SDBF),
characterized in that
(f) "n" reference subdata bits (S-SDB) are assigned to at least one reference data bit (S-DB),

(g) of the reference data bits (S-DB) with the "n" reference subdata bits (S-SDB), one reference data bit (S-DB) contains "Don't Care Bits" (DCB) of the 1st order (**), which
(g1) are arranged in the reference data bit (S-DB) in such a way that bit transitions between the reference data bit (S-DB) containing the "Don't Care Bits" (DCB) of the 1st order (**) and adjacent reference data bits (S-DB) are detected, and

(g2) are evaluated in such a way that the occurrence of a specific group of bit combinations of the "Don't Care Bits" (DCB) of the 1st order (**) is used as a check for the sampling phase (APH) located in the centre of the data bit and the actual subdata bit sequences (I-SDBF) are compared as a function thereof with the reference subdata bit sequence (S-SDBF).
Sampling method according to Claim 1, characterized in that the reference data stream component (S-DS) is defined as an "H-L-H" bit sequence of the reference data bits (S-DB).
Sampling method according to Claim 1, characterized in that the reference data stream component (S-DS) is defined as an "L-H-L" bit sequence of the reference data bits (S-DB).
Sampling method according to one of Claims 1 to 3, characterized in that three of the "n" reference subdata bits (S-SDB) of the reference data bit (S-DB), a first reference subdata bit (S-SDB₁), a (n-1)-th reference subdata bit (S-SDB_n-1) and an n-th reference subdata bit (S-SDB_n), are defined as "Don't Care Bits" (DCB) of the 1st order (**).
Sampling method according to Claims 1, 3 and 4, characterized in that the specific group of bit combinations formed by the first reference subdata bit (S-SDB₁), the (n-1)-th reference subdata bit (S-SDB_n-1) and the n-th reference subdata bit (S-SDB_n) contains the following bit combinations: 0 0 0 0 1 0 1 1 0 1 1 1
Sampling method according to Claims 1, 2 and 4, characterized in that the specific group of bit combinations formed by the first reference subdata bit (S-SDB₁), the (n-1)-th reference subdata bit (S-SDB_n-1) and the n-th reference subdata bit (S-SDB_n) contains the following bit combinations: 1 1 1 1 0 1 0 0 1 0 0 0
Sampling method according to one of Claims 1 to 6, characterized in that the determined sampling phase (APH) for the synchronization of the digital data stream (DS) is retained if the comparisons between the actual subdata bit sequences (I-SDBF) and the reference subdata bit sequence (S-SDBF) supply "m with m < n" correspondences.
Use of the sampling method according to one of Claims 1 to 7 in a cordless telecommunications device.
Sampling device, having
(a) first means (141) for generating subdata bits (SDB) by means of n-fold sampling of a data stream component (SY-EW), which is relevant to synchronization, of a digital data stream (DS),

(b) second means (1400...1402) for buffering subdata sequences (I-SDBF) with a plurality of actual subdata bits (I-SDB),
(b1) the actual subdata bits (I-SDB) being produced by virtue of the fact that the first means (141) sample actual data bits (I-DB) of an actual data stream component (I-DS),

(b2) the first and second means (141, 1400...1402) are connected to one another in such a way that the actual subdata bit sequence (I-SDBF) is changed with every sampling by storing a new actual subdata bit (I-SDB) and deleting the actual subdata bit (I-SDB) which has been buffered the longest,

(c) third means (1403, 1404, 1421, 1422) for determining a sampling phase (APH), which are connected to the first and second means (141, 1400...1402) and are constructed in such a way that
(c1) the buffered actual subdata bit sequences (I-SDBF) are compared with a reference subdata bit sequence (S-SDBF) of reference subdata bits (S-SDB) which are assigned to at least two successive reference data bits (S-DB) of a reference data bit component (S-DS),

(c2) the sampling phase (APH) is determined if the actual subdata bit sequence (I-SDBF) corresponds to the reference subdata bit sequence (S-SDBF),

characterized in that
(d) the reference subdata bit sequence (S-SDBF) is constructed in such a way that "n" reference subdata bits (S-SDB) are assigned to at least one reference data bit (S-DB), of the reference data bits (S-DB) with the "n" reference subdata bits (S-SDB), one reference data bit (S-DB) containing "Don't Care Bits" (DCB) of the 1st order (**),

(e) the "Don't Care Bits" (DCB) of the 1st order (**) are arranged in the reference data bit (S-DB) in such a way that bit transitions between the reference data bit (S-DB) containing the "Don't Care Bits" (DCB) of the 1st order (**) and adjacent reference data bits (S-DB) are detected,

(f) the "Don't Care Bits" (DCB) of the 1st order (**) are evaluated in such a way that the occurrence of a specific group of bit combinations of the "Don't Care Bits" (DCB) of the 1st order (**) is used as a check for the sampling phase (APH) located in the centre of the data bit and the actual subdata bit sequences (I-SDBF) are compared as a function thereof with the reference subdata bit sequence (S-SDBF).
Sampling device according to Claim 10, characterized in that the third means (1403, 1404, 1421, 1422) for determining the sampling phase (APH) are realized as a gate logic in an ASIC module.
Cordless telecommunications device, in particular a base station (BS) or a mobile station (MS), having a sampling device (140) according to Claim 9 or 10 integrated in a control device (14), characterized in that bit identity detection means (1420) are provided, which means (1420) are connected on the input side to the first means (1400...1402) and on the output sides to the third means (1403, 1404, 1421, 1422) and which transmit a control signal (ZS) to the third means (1403, 1404, 1421, 1422) when two identical actual data bits (I-DB) are detected in the first means (1400...1402), which third means retain the sampling phase (APH) if "m" comparison correspondences have already been counted.
Cordless telecommunications device according to Claim 11, characterized in that noise detection means (143) are provided which are connected on the input side to the first means (1400...1402) and on the output side to the third means (1403, 1404, 1421, 1422) and which, in the event of actual data bits (I-DB) which are buffered in the first means (1400...1402) being subject to noise reset the third means (1403, 1404, 1421, 1422) activated by these data bits (I-DB), in order to fix the sampling phase (APH).