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FR2977073B1 - Procede de transfert d'une couche de semi-conducteur, et substrat comprenant une structure de confinement - Google Patents

Procede de transfert d'une couche de semi-conducteur, et substrat comprenant une structure de confinement

Info

Publication number
FR2977073B1
FR2977073B1 FR1155577A FR1155577A FR2977073B1 FR 2977073 B1 FR2977073 B1 FR 2977073B1 FR 1155577 A FR1155577 A FR 1155577A FR 1155577 A FR1155577 A FR 1155577A FR 2977073 B1 FR2977073 B1 FR 2977073B1
Authority
FR
France
Prior art keywords
transferring
substrate
semiconductor layer
containment structure
containment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1155577A
Other languages
English (en)
Other versions
FR2977073A1 (fr
Inventor
Fabrice Lallement
Christophe Figuet
Daniel Delprat
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to FR1155577A priority Critical patent/FR2977073B1/fr
Priority to PCT/EP2012/061848 priority patent/WO2012175561A1/fr
Priority to US14/127,926 priority patent/US9716029B2/en
Priority to TW101122492A priority patent/TWI630642B/zh
Publication of FR2977073A1 publication Critical patent/FR2977073A1/fr
Application granted granted Critical
Publication of FR2977073B1 publication Critical patent/FR2977073B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82Heterojunctions

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
FR1155577A 2011-06-23 2011-06-23 Procede de transfert d'une couche de semi-conducteur, et substrat comprenant une structure de confinement Active FR2977073B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FR1155577A FR2977073B1 (fr) 2011-06-23 2011-06-23 Procede de transfert d'une couche de semi-conducteur, et substrat comprenant une structure de confinement
PCT/EP2012/061848 WO2012175561A1 (fr) 2011-06-23 2012-06-20 Procédé de transfert d'une couche de semi-conducteur et substrat comprenant une structure de confinement
US14/127,926 US9716029B2 (en) 2011-06-23 2012-06-20 Method for transferring a layer of a semiconductor and substrate comprising a confinement structure
TW101122492A TWI630642B (zh) 2011-06-23 2012-06-22 用以移轉半導體層之方法與包含限制結構之基體

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1155577A FR2977073B1 (fr) 2011-06-23 2011-06-23 Procede de transfert d'une couche de semi-conducteur, et substrat comprenant une structure de confinement

Publications (2)

Publication Number Publication Date
FR2977073A1 FR2977073A1 (fr) 2012-12-28
FR2977073B1 true FR2977073B1 (fr) 2014-02-07

Family

ID=46321017

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1155577A Active FR2977073B1 (fr) 2011-06-23 2011-06-23 Procede de transfert d'une couche de semi-conducteur, et substrat comprenant une structure de confinement

Country Status (4)

Country Link
US (1) US9716029B2 (fr)
FR (1) FR2977073B1 (fr)
TW (1) TWI630642B (fr)
WO (1) WO2012175561A1 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2995447B1 (fr) 2012-09-07 2014-09-05 Soitec Silicon On Insulator Procede de separation d'au moins deux substrats selon une interface choisie
JP6511516B2 (ja) * 2014-05-23 2019-05-15 マサチューセッツ インスティテュート オブ テクノロジー ゲルマニウム・オン・インシュレータ基板の製造方法
FR3077923B1 (fr) * 2018-02-12 2021-07-16 Soitec Silicon On Insulator Procede de fabrication d'une structure de type semi-conducteur sur isolant par transfert de couche
FR3099637B1 (fr) 2019-08-01 2021-07-09 Soitec Silicon On Insulator procédé de fabrication d’unE structure composite comprenant une couche mince en Sic monocristallin sur un substrat support en sic polycristallin
KR102250895B1 (ko) * 2019-12-23 2021-05-12 주식회사 현대케피코 반도체 소자의 제조방법
FR3144390A1 (fr) * 2022-12-27 2024-06-28 Commissariat A L' Energie Atomique Et Aux Energies Alternatives Procédé de transfert de couche semiconductrice

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998059365A1 (fr) 1997-06-24 1998-12-30 Massachusetts Institute Of Technology REGULATION DES DENSITES DE DISLOCATION FILETEES DANS DES DISPOSITIFS GERMANIUM SUR SILICIUM AU MOYEN DE COUCHES A TENEUR ECHELONNEE EN GeSi ET D'UNE PLANARISATION
US6890835B1 (en) * 2000-10-19 2005-05-10 International Business Machines Corporation Layer transfer of low defect SiGe using an etch-back process
US6649492B2 (en) * 2002-02-11 2003-11-18 International Business Machines Corporation Strained Si based layer made by UHV-CVD, and devices therein
US6995430B2 (en) 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US6953736B2 (en) * 2002-07-09 2005-10-11 S.O.I.Tec Silicon On Insulator Technologies S.A. Process for transferring a layer of strained semiconductor material
WO2004021420A2 (fr) * 2002-08-29 2004-03-11 Massachusetts Institute Of Technology Systeme de fabrication ameliore et procede pour semi-conducteur monocristallin sur un substrat
US7202124B2 (en) * 2004-10-01 2007-04-10 Massachusetts Institute Of Technology Strained gettering layers for semiconductor processes
US10374120B2 (en) * 2005-02-18 2019-08-06 Koninklijke Philips N.V. High efficiency solar cells utilizing wafer bonding and layer transfer to integrate non-lattice matched materials
TW200707799A (en) * 2005-04-21 2007-02-16 Aonex Technologies Inc Bonded intermediate substrate and method of making same
JP2009532918A (ja) * 2006-04-05 2009-09-10 シリコン ジェネシス コーポレーション レイヤトランスファプロセスを使用する太陽電池の製造方法および構造
EP2333824B1 (fr) * 2009-12-11 2014-04-16 Soitec Fabrication de dispositifs SOI mince
US8163581B1 (en) * 2010-10-13 2012-04-24 Monolith IC 3D Semiconductor and optoelectronic devices
US8196546B1 (en) * 2010-11-19 2012-06-12 Corning Incorporated Semiconductor structure made using improved multiple ion implantation process

Also Published As

Publication number Publication date
FR2977073A1 (fr) 2012-12-28
TWI630642B (zh) 2018-07-21
US20140183601A1 (en) 2014-07-03
WO2012175561A1 (fr) 2012-12-27
TW201308397A (zh) 2013-02-16
US9716029B2 (en) 2017-07-25

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