FR2340620A1 - MANUFACTURING PROCESS OF A LARGE-SCALE INTEGRATED DEVICE HAVING A FLAT SURFACE - Google Patents

MANUFACTURING PROCESS OF A LARGE-SCALE INTEGRATED DEVICE HAVING A FLAT SURFACE

Info

Publication number: FR2340620A1
Authority: FR; France
Prior art keywords: manufacturing process; flat surface; integrated device; scale integrated; scale
Prior art date: 1976-02-06
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Granted

Application number

FR7639828A

Other languages

French (fr)

Other versions

FR2340620B1 (en

Inventor

Ekkehard F Miersch

Hwa N Yu

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

International Business Machines Corp

Original Assignee

International Business Machines Corp

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1976-02-06

Filing date

1976-12-30

Publication date

1977-09-02

1976-12-30 Application filed by International Business Machines Corp filed Critical International Business Machines Corp

1977-09-02 Publication of FR2340620A1 publication Critical patent/FR2340620A1/en

1979-09-28 Application granted granted Critical

1979-09-28 Publication of FR2340620B1 publication Critical patent/FR2340620B1/fr

Status Granted legal-status Critical Current

Links

238000004519 manufacturing process Methods 0.000 title 1

Classifications

- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/7688—Filling of holes, grooves or trenches, e.g. vias, with conductive material by deposition over sacrificial masking layer, e.g. lift-off

Landscapes

Engineering & Computer Science (AREA)
Physics & Mathematics (AREA)
Condensed Matter Physics & Semiconductors (AREA)
General Physics & Mathematics (AREA)
Manufacturing & Machinery (AREA)
Computer Hardware Design (AREA)
Microelectronics & Electronic Packaging (AREA)
Power Engineering (AREA)
Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Weting (AREA)
Electrodes Of Semiconductors (AREA)

FR7639828A 1976-02-06 1976-12-30 MANUFACTURING PROCESS OF A LARGE-SCALE INTEGRATED DEVICE HAVING A FLAT SURFACE Granted FR2340620A1 (en)

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
US65581476A	1976-02-06	1976-02-06

Publications (2)

Publication Number	Publication Date
FR2340620A1 true FR2340620A1 (en)	1977-09-02
FR2340620B1 FR2340620B1 (en)	1979-09-28

Family

ID=24630480

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
FR7639828A Granted FR2340620A1 (en)	1976-02-06	1976-12-30	MANUFACTURING PROCESS OF A LARGE-SCALE INTEGRATED DEVICE HAVING A FLAT SURFACE

Country Status (6)

Country	Link
JP (1)	JPS5827664B2 (en)
CA (1)	CA1088382A (en)
DE (1)	DE2703473A1 (en)
FR (1)	FR2340620A1 (en)
GB (1)	GB1521431A (en)
IT (1)	IT1079545B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
EP0008359A2 (en) *	1978-08-21	1980-03-05	International Business Machines Corporation	Process for making a thin-film structure

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JPS59170692A (en) *	1983-03-16	1984-09-26	Ebara Corp	Water-sealed heat exchanger
US11129289B2 (en)	2015-10-27	2021-09-21	Schaeffler Technologies AG & Co. KG	Bearing assembly with incorporated electric line for providing multiple operating voltages

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
DE1267738B (en) *	1962-10-29	1968-05-09	Intellux Inc	Process for making electrical connections between the circuits of multilayer printed electrical circuits
US3464855A (en) *	1966-09-06	1969-09-02	North American Rockwell	Process for forming interconnections in a multilayer circuit board
DE1765013A1 (en) *	1968-03-21	1971-07-01	Telefunken Patent	Process for the production of multilevel circuits
DE2059425A1 (en) *	1970-12-02	1972-06-22	Siemens Ag	Partial structure of printed multilayer circuits
JPS4960870A (en) *	1972-10-16	1974-06-13
US3873361A (en) *	1973-11-29	1975-03-25	Ibm	Method of depositing thin film utilizing a lift-off mask
JPS5120681A (en) *	1974-07-27	1976-02-19	Oki Electric Ind Co Ltd	Handotaisochino seizohoho
NL7415841A (en) *	1974-12-05	1976-06-09	Philips Nv	PROCESS FOR THE MANUFACTURE OF A SEMI-CONDUCTOR DEVICE AND SEMI-CONDUCTOR DEVICE, MANUFACTURED ACCORDING TO THE PROCESS.
JPS5272571A (en) *	1975-12-15	1977-06-17	Fujitsu Ltd	Production of semiconductor device

1976
- 1976-12-30 FR FR7639828A patent/FR2340620A1/en active Granted
1977
- 1977-01-19 JP JP52004049A patent/JPS5827664B2/en not_active Expired
- 1977-01-19 GB GB205677A patent/GB1521431A/en not_active Expired
- 1977-01-28 DE DE19772703473 patent/DE2703473A1/en active Granted
- 1977-01-28 IT IT1972177A patent/IT1079545B/en active
- 1977-02-03 CA CA271,002A patent/CA1088382A/en not_active Expired

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
EP0008359A2 (en) *	1978-08-21	1980-03-05	International Business Machines Corporation	Process for making a thin-film structure
EP0008359A3 (en) *	1978-08-21	1980-03-19	International Business Machines Corporation	Process for making a thin-film structure

Also Published As

Publication number	Publication date
JPS5295987A (en)	1977-08-12
IT1079545B (en)	1985-05-13
JPS5827664B2 (en)	1983-06-10
DE2703473A1 (en)	1977-08-11
GB1521431A (en)	1978-08-16
DE2703473C2 (en)	1991-01-24
CA1088382A (en)	1980-10-28
FR2340620B1 (en)	1979-09-28

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Legal Events

Date	Code	Title	Description
1991-10-25	ST	Notification of lapse