DE3153249C2 - Phase discriminator arrangement - Google Patents

Abstract

The invention relates to a phase discriminator arrangement for generating a control voltage depending on the phase difference between a line pulse and a clock pulse, in a regenerative repeater of a pulse code modulation multiplex transmission system, the line pulse being a line signal formed in accordance with a ternary code and exhibiting pulses of a first polarity and pulses of a second polarity. The arrangement consists of two phase discriminators, one for the pulses of the first polarity and one for the pulses of the second polarity. Each phase discriminator is constructed in such a manner that it operates correctly even when the length of the pulses and interpulse spaces of the line pulse is an integral multiple of the period of the clock pulse. This also results in correct operation with relatively long sequences of "ones".

Description

The invention relates to a phase discriminator arrangement according to the preambles of claims 1 and 2, respectively.

In the transmission paths of pulse code modulation multiplex Transmission systems are inserted intermediate regenerators, that regenerate the line signal. This is a clock pulse needed, its edges to the edges of the power signal have a certain phase position. It is from the Magazine ′ ′ Technical communications AEG-TELEFUNKEN, supplement New developments in the field of PCM technology, Berlin 1974 '', page 17 and 18 known, this clock pulse in to generate a local voltage controlled oscillator whose frequency with a through a phase discriminator Controlled voltage obtained from the line signal controlled becomes. The line signal is after a ternary code formed, d. H. it has positive and negative impulses. A sum signal is obtained and this one Phase discriminator fed. This principle only works correct if the impulses and pauses of the line signal or the line pulse obtained therefrom are not shorter than 0.6 times and not longer than 1.4 times the length of a period of the clock pulse. It also fails with longer ′ ′ ones ′ ′ - consequences.

The invention has for its object a phase discriminator arrangement of the type mentioned at the beginning, that the nominal values of the pulse and pause lengths of the Line pulse integer multiples of the period of the Clock pulses can be, with pulses and pauses with different integer multiples in any Order can occur. The actual impulses and Break lengths can be up to 0.4 times the period  of the clock pulse differ from their nominal values. Further should be correct with any length '' ones '' - sequences Work must be guaranteed.

This task is characterized by the characteristics of the Claim 1 and 2 solved.

The training according to claim 3 is a reduction the power consumption achieved.

The invention is explained below with reference to the exemplary embodiments shown in FIGS. 1 to 11.

In Fig. 1 a Phasendiskriminatoranordnung is prepared according to the patent claim 1, whose functions will be explained with reference to FIGS. 2 to 5. FIG. 6 shows a phase discriminator arrangement according to claim 2. FIG. 7 shows a phase discriminator arrangement according to claim 1, which was further developed according to claim 3 and whose functions are explained with reference to FIGS. 8 to 10. The Fig. 11 refers to a Phasendiskriminatoranordnung according to claim 2, which was further formed according to the claim 3.

It mean in Fig. 1:

First phase discriminator:

E = line pulse input FF 1 , FF 2 = first or second delay flip-flop with data input D 1 or D 2 , clock input C 1 or C 2 and non-inverting output Q 1 or Q 2 , 1, 2 = First or second exclusive-OR gate, S 1 , S 2 = first or second constant current source,

Second phase discriminator:

E 1 = line pulse input FF 11 , FF 12 = first or second delay flip-flop with data input D 11 or D 12 , clock input C 11 or C 12 and non-inverting output Q 11 or Q 12 , 11, 12 = First or second exclusive-OR gate, S 11 , S 12 = first or second constant current source,

common to both phase discriminators:

T = clock pulse input, C = capacitor, A = control voltage output.

In a manner not shown here, a line pulse is obtained from the positive pulses of the line signal and is supplied to the line pulse input E. Likewise, a further line pulse is obtained from the negative pulses of the line signal, which line is converted by a converter (not shown) connected upstream of the second phase discriminator so that positive pulses also appear at line pulse input E 1 . With the control voltage appearing at the control voltage output A , the frequency of the local voltage-controlled oscillator is controlled, the output signal of which is supplied to the clock pulse input T.

The delay flip-flops as well as the exclusive-OR gates with positive operating voltage compared to the reference potential (ground) operated. Accordingly, positive means Voltage on signal lines yes signal or pulse.

A delay flip-flop takes over a positive one right now Clock edge at that moment at its data input lying state. An exclusive-OR gate gives a yes signal at its output if at both of them Different logic signals are present at the inputs.  

The inputs of the constant current sources S 1 , S 2 , S 11 and S 12 are connected to the outputs of the exclusive-OR gates 1, 2, 11 and 12 , respectively. They only give a constant current I ₁, I ₂, I ₁₁ or I ₁₂ at their outputs if there are logical yes signals at their inputs. If there are logical no signals at the inputs, the outputs have very high resistance values.

The current I ₁ or I ₁₁ is driven by a positive voltage relative to the reference potential, the current I ₂ or I ₁₂ provides a voltage source with a negative voltage. Except that the capacitor C is initially charged negatively, ie the control voltage output A has a negative potential with respect to the reference potential, the capacitor C is first discharged by the current I ₁ or I ₁₁ and then charged positively. Through a current I ₂ or I ₁₂, the capacitor, if it is positively charged, is also initially discharged and then charged negatively. If none of the constant current sources supplies a current, the capacitor maintains its charge state, ie the voltage at the control voltage output remains constant, provided the downstream device has a sufficiently high input resistance.

The function of the phase discriminator arrangement is then explained on the basis of FIGS. 2 to 5, in which the assignment of the individual curves to the lines and inputs and outputs of FIG. 1 is indicated by identical names. The curves designated a and b relate to the outputs of the exclusive-OR gates 1 and 2 , respectively, with a being assigned to the exclusive-OR gate 1 . In FIGS. 2 to 5 and in the following text only the first phase discriminator is described, but the descriptions apply mutatis mutandis to the second phase discriminator, because this is like the first in design and function.

In Fig. 2 is until the time t ₁ the case of the line pulse (curve E) are as long as a period of the clock pulse (curve T) and that the edges of the line pulse coincide with the negative edges of the clock pulse. As a result, the constant current source S 1 is alternately effective and ineffective for the same length. The constant current source S 2 is continuously controlled effectively. Since the current I ₂ supplied by it is half the size and reversed in the direction of the current I 1 supplied by the constant current source S 1 , the capacitor C is alternately charged and discharged positively and negatively. The control voltage (curve A) therefore changes by 0 volts.

After the time t ₁, the line pulse has pulses and pauses that are somewhat shorter than a period of the clock pulse. As a result, the time periods in which the capacitor is charged in the positive direction become longer and longer, while the discharge times become shorter and shorter. As a result, the control voltage assumes ever larger positive values.

Fig. 3 agrees up to the time t ₂ with the corresponding part of FIG. 2. After the time t ₂, the line pulse consists of pulses and pauses that are slightly longer than a period of the clock pulse. As a result, the control voltage takes on ever larger negative values.

In FIG. 4, the operations are illustrated with a line pulse, the pulses and pauses with exactly the double and triple length having a period of the clock pulse. Up to the time t ₃ occur pulses and pauses in the line pulse, which have the same length as a period of the clock pulse, that is, this part of FIG. 4 corresponds to the corresponding parts of FIGS. 2 and 3. After the time t ₃ occurs first a pause and a pulse with twice the length, later a pause and a pulse with three times the length of a period of the clock pulse. Since the position of the edges of the line pulse coincides with the negative edges of the clock pulse before the time t ₃, each edge of the line pulse coincides with a negative edge of the clock pulse even after the time t ₃.

In contrast to the processes in FIGS. 2 and 3, periods of time also occur here in which none of the constant current sources or the constant current source S 1 is effective alone. In the first case, e.g. B. between the times t ₄ and t ₅, the voltage across the capacitor C remains constant, in the second case, for. B. between times t ₅ and t ₆, it changes twice as fast as in the case in which both constant current sources are effective. Since time periods alternate with charges and discharges with changing polarity but the same voltage amounts, the control voltage changes by 0 volts, which results in a negative mean value.

Fig. 5 differs from Fig. 4 in that the first longer pause of the line pulse (after the time t ₇) is not exactly but a little less than twice as long as a period of the clock pulse. As a result, all subsequent edges of the line pulse no longer coincide with the associated negative edges of the clock pulse. This causes the capacitor to be charged more positively than negatively and the mean value of the control voltage takes on ever larger positive values.

Since not only the outputs of the constant current sources of the first phase discriminator but also those of the second phase discriminator are connected to the capacitor C and positive and negative pulses occur alternately in a ternary line signal, the charging or discharging of the capacitor also becomes negative in a manner not shown Impulses affected. In this way, the pulses of both polarities are used to obtain the control voltage.

In the exemplary embodiment according to FIG. 6, the constant current sources of the exemplary embodiment according to FIG. 1 are replaced by series connections made up of resistors and diodes, the following assignment existing:

first series circuit R 1 , GR 1 first phase discriminator second series circuit R 2 , GR 2 first phase discriminator first series circuit R 11 , GR 11 second phase discriminator second series circuit R 12 , GR 12 second phase discriminator

The resistors R 1 and R 11 have half the resistance value compared to the resistors R 2 and R 12 .

Since the delay flip-flops and the exclusive-OR gates are operated with a voltage which is positive with respect to the reference potential (ground), the capacitor C is switched via the diode GR in the event of a logical yes signal at the output of the exclusive-OR gate 1 or 11 1 or GR 11 and the resistor R 1 or R 11 loaded. In the event of a logical no signal at the output of the exclusive-OR gate 2 or 12 , the capacitor C is discharged via the diode GR 2 or GR 12 and the resistor R 2 or R 12 .

Logical yes signal at the output of the exclusive-OR gate 1 or 11 thus corresponds to the state of the activated constant current source S 1 or S 11 in FIG. 1. In contrast, the state of the activated constant current source S 2 or S 12 corresponds to one no signal at the output of the exclusive-OR gate 2 or 12 of FIG. 6, which by connecting its second input to the inverting output or (instead of the non-inverting output Q 2 or Q 12 of FIG. 1) of second delay flip-flops is reached.

Taking into account the aforementioned deviations, FIGS. 2 to 5 can also be used to explain the function of a phase discriminator arrangement according to FIG. 6. It should also be noted that if the phase relationship coincides (before the times t ₁, t ₂ and t ₇ of Fig. 2, 3 and 5), the control voltage fluctuates by a value which corresponds to half the operating voltage.

In the phase discriminators according to FIGS. 1 and 6, both delay flip-flops must have signal propagation times which are negligibly short compared to the clock pulse period. Short signal propagation times are associated with high power consumption, so that a phase discriminator which can be used at a high clock pulse frequency has a high power consumption. The training according to claim 3 aims to reduce the power consumption.

By inserting a third delay flip-flop achieved that only the signal delay of the first delay Flip flops must be negligibly short compared to the clock pulse period. The signal delays of the second and third Delay flip-flops only have to be identical to one another. So that's enough it, for the first delay flip-flop one of a family of circuits with a short signal runtime but high power consumption select, e.g. B. one from the TTL standard Series. Such are sufficient for the second and third delay flip-flops with lower power consumption, but longer signal runtime, e.g. B. from the TTL low-power series. Despite the The additional effort of a delay flip-flop results in a reduction of power consumption since two delay flip-flops the TTL low-power series has a lower power consumption have as one of the TTL standard series.  

In FIG. 7, a phase discriminator being characterized by the patent claim 1 which has been further developed, according to claim 3 as described above. In the processing between the non-inverting output Q 1 or Q 11 of the first delay flip-flop FF 1 or FF 11 and the data input D 2 or D 12 of the second delay flip-flop FF 2 or FF 12 , a third delay Flip-flop FF 3 or FF 13 inserted, the non-inverting output Q 1 or Q 11 of the first delay flip-flop FF 1 or FF 11 with the data input D 3 or D 13 of the third delay flip-flop FF 3 or FF 13 and its non-inverting output Q 3 or Q 13 is connected to the data input D 2 or D 12 of the second delay flip-flop FF 2 or FF 12 . The clock input C 3 or C 13 of the third delay flip-flop FF 3 or FF 13 is connected to the clock pulse input T. The other details correspond to those of FIG. 1.

The function is described with reference to FIGS. 8 to 10, which essentially correspond to FIGS. 2, 4 and 5, with only the first phase discriminator being described here as in the first exemplary embodiment. The difference is that a curve is drawn for the signal at the non-inverting output Q 3 of the third delay flip-flop FF 3 and the signal propagation time t _{L of} these two delays as well as for the signal at the non-inverting output Q 2 of the second delay flip-flop FF 2 -Flip flops was taken into account.

In Fig. 8, the processes when the line pulse edges coincide with the negative clock pulse edges were shown as in Fig. 2 until time t ₁. After the time t ₁, shorter line pulse periods occur, which, as in FIG. 2, results in an increase in the control voltage after positive values.

If longer power periods occur, as shown in FIG. 3, the control voltage also takes on ever larger negative values in this phase discriminator. It was not shown in a separate figure.

In FIG. 9, as in FIG. 4, the processes are shown with a line pulse which has pulses and pauses with exactly twice and three times the length of a period of the clock pulse. Up to the time t ₃ occur pulses and pauses in the line pulse, which have the same length as a period of the clock pulse, that is, this part of FIG. 9 corresponds to the corresponding part of FIG. 8. After the time t ₃ occurs first a pause and a pulse with twice the length, later a pause and a pulse with three times the length of a period of the clock pulse. Since due to the insertion of the third delay flip-flop FF 3, the second constant current source S 2 during the long pulses and pauses (after the time t ₃) by a clock pulse period and the signal delay t _{L is} later deactivated (time t ₈), the control voltage takes one somewhat larger negative mean than in the case of FIG. 4.

Fig. 10 differs from Fig. 9 in that the first longer pause of the line pulse (after the time t ₉) is not exactly but a little less than twice as long as a period of the clock pulse. As a result, as in FIG. 5, all subsequent edges of the line pulse no longer coincide with the associated negative edges of the clock pulse. This causes the capacitor to be charged more positively than negatively, so that the mean value of the control voltage assumes ever larger positive values. Here, too, as explained in the description of the exemplary embodiment according to FIG. 1, the charge or discharge of the capacitor C is controlled by the negative pulses of the line signal via the second phase discriminator.

Fig. 11 shows a phase discriminator arrangement according to claim 2, which are further developed according to claim 3. The difference compared to FIG. 6 is that between the first delay flip-flops FF 1 and FF 11 and the second delay flip-flops FF 2 and FF 12 , third delay flip-flops FF 3 and FF 13 , respectively, in the same Way as shown in Fig. 7 are inserted. Thus, the descriptions for FIGS. 6 and 7 also apply analogously to FIG. 11.

Claims (12)

1. A phase discriminator arrangement for generating a control voltage dependent on the phase difference between a line pulse and a clock pulse in an intermediate regenerator of a pulse code modulation multiplex transmission system, the line pulse being a line signal formed according to a ternary code and having pulses of a first polarity and pulses of a second polarity, characterized in that a first phase discriminator (FF 1 , FF 2 , 1, 2, S 1 , S 2 ) for the pulses of the first polarity and a second, identical phase discriminator (FF 11 , FF 12, 11, 12, S 11 , S 12 ) is provided for the pulses of the second polarity,
that each phase discriminator has:

• - a line pulse input (E or E 1 ),
• a first (FE 1 or FF 11 ) and a second (FF 2 or FF 12 ) delay flip-flop,
• a first ( 1 or 11 ) and a second ( 2 or 12 ) exclusive-OR gate,
• a first (S 1 or S 11 ) and a second (S 2 or S 12 ) constant current source,

that for both phase discriminators are common:

• - a clock pulse input (T) ,
• - a control voltage output (A),
• - a capacitor (C),

that one of the two phase discriminators is preceded by a converter that changes the polarity of the pulses, so that the pulses of the line signal appear at the line pulse input (E) of the first phase discriminator with the same polarity as at the line pulse input (E 1 ) of the second phase discriminator, that is connected:

• the clock pulse input (T) with the clock inputs (C 1 , C 2 , C 11 , C 12 ) of all delay flip-flops,
• - the control voltage output (A) with the outputs of all constant current sources and the first coating of the capacitor (C),
• - the second coating of the capacitor (C) with the reference potential,

that in each phase discriminator is connected:

• - The line pulse input (E or E 1 ) with the data input (D 1 or D 11 ) of the first delay flip-flop (FF 1 or FF 11 ) and the first input of the first exclusive-OR gate ( 1 or 11 ),
• the non-inverting output (Q 1 or Q 11 ) of the first delay flip-flop (FF 1 or FF 11 ) with the second input of the first exclusive-OR gate ( 1 or 11 ),
• the data input (D 2 or D 12 ) of the second delay flip-flop (FF 2 or FF 12 ) with the first input of the second exclusive-OR gate ( 2 or 12 ),
• - the non-inverting output (Q 2 or Q 12 ) of the second delay flip-flop (FF 2 or FF 12 ) with the second input of the second exclusive-OR gate ( 2 or 12 ),
• the output of the first exclusive-OR gate ( 1 or 11 ) with the input of the first constant current source (S 1 or S 11 ),
• the output of the second exclusive-OR gate ( 2 or 12 ) with the input of the second constant current source (S 2 or S 12 ),

that in each phase discriminator a connection between the non-inverting output (Q 1 or Q 11 ) of the first delay flip-flop (FF 1 or FF 11 ) and the data input (D 2 or D 12 ) of the second delay flip-flop (FF 2 or FF 12 ) is that each constant current source is designed so that its outputs only give constant currents (I ₁, I ₂, I ₁₁, I ₁₂) when logical yes signals are present at their inputs, but when logical no Signals have an infinitely high resistance and that the constant current (I ₁ or I ₁₁) of the first constant current source (S 1 or S 11 ) double the value and vice versa polarity compared to that of the second constant current source (S 2 or S 12 ) delivered current (I ₂ or I ₁₂) ( Fig. 1). 2. A phase discriminator arrangement for generating a control voltage dependent on the phase difference between a line pulse and a clock pulse in an intermediate generator of a pulse code modulation multiplex transmission system, the line pulse being a line signal formed according to a ternary code and having pulses of a first polarity and pulses of a second polarity, characterized in that a first phase discriminator (FF 1 , FF 2, 1, 2, GR 1 , GR 2 , R 1 , R 2 ) for the pulses of the first polarity and a second, identical phase discriminator (FF 11 , FF 12, 11 , 12, GR 11 , GR 12 , R 11 , R 12 ) is provided for the pulses of the second polarity that each phase discriminator has:

• - a line pulse input (E or E 1 ),
• a first (FF 1 or FF 11 ) and a second ( FF 2 or FF 12 ) delay flip-flop,
• a first ( 1 or 11 ) and a second ( 2 or 12 ) exclusive-OR gate,
• a first series circuit comprising a first diode (GR 1 or GR 11 ) and a first resistor (R 1 or R 11 ),
• a second series circuit comprising a second diode (GR 2 or GR 12 ) and a second resistor (R 2 or R 12 ),

that for both phase discriminators are common:

• - a clock pulse input (T),
• - a control voltage output (A),
• - a capacitor (C),

that one of the two phase discriminators is preceded by a converter which changes the polarity of the pulses, so that the pulses of the line signal appear at the line pulse input (E) of the first phase discriminator with the same polarity as at the line pulse input (E 1 ) of the second phase discriminator, that is connected:

• the clock pulse input (T) with the clock inputs (C 1 , C 2 , C 11 , C 12 ) of all delay flip-flops,
• - the control voltage output (A) with the second connections of all series connections and the first coating of the capacitor (C),
• - the second coating of the capacitor (C) with the reference potential,

that in each phase discriminator is connected:

• - The line pulse input (E or E 1 ) with the data input (D 1 or D 11 ) of the first delay flip-flop (FF 1 or FF 11 ) and the first input of the first exclusive-OR gate ( 1 or 11 ),
• the non-inverting output (Q 1 or Q 11 ) of the first delay flip-flop (FF 1 or FF 11 ) with the second input of the first exclusive-OR gate ( 1 or 11 ),
• the data input (D 2 or D 12 ) of the second delay flip-flop (FF 2 or FF 12 ) with the first input of the second exclusive-OR gate ( 2 or 12 ),
• - The inverting output (or) of the second delay flip-flop (FF 2 or FF 12 ) with the second input of the second exclusive-OR gate ( 2 or 12 )
• the output of the first exclusive-OR gate ( 1 or 11 ) with the first connection of the first series connection,
• - The output of the second exclusive-OR gate ( 2 or 12 ) with the first connection of the second series connection

that in each phase discriminator a connection between the non-inverting output (Q 1 or Q 11 ) of the first delay flip-flop (FF 1 or FF 11 ) and the data input (D 2 or D 12 ) of the second delay flip-flop (FF 2 or FF 12 ) is that the first resistor (R 1 or R 11 ) compared to the second resistor (R 2 or R 12 ) has half the resistance value and that the diodes are polarized so that they can be controlled when the the first exclusive-OR gates ( 1 and 11 ) deliver the logical yes signals and the second exclusive-OR gates ( 2 and 12 ) the voltages corresponding to the logical no signals ( FIG. 6). 3. phase discriminator arrangement according to claim 1 or 2, characterized in that in the connections between the non-inverting outputs (Q 1 or Q 11 ) of the first delay flip-flops (FF 1 or FF 11 ) and the data inputs (D 2 or D 12 ) of the second delay flip-flops (FF 2 or FF 12 ) third delay flip-flops (FF 3 or FF 13 ) are inserted, with the following being connected:

• the non-inverting outputs (Q 1 or Q 11 ) of the first delay flip-flops (FF 1 or FF 11 ) with the data inputs (D 3 or D 13 ) of the third delay flip-flops,
• - The non-inverting outputs (Q 3 or Q 13 ) of the third delay flip-flops (FF 3 or FF 13 ) with the data inputs (D 2 or D 12 ) of the second delay flip-flops (FF 2 or FF 12 ) ,
• - the clock inputs (C 3 or FF 13 ) with the clock pulse input (T),

and that the respective second delay flip-flop (FF 2 or FF 12 ) and respective third delay flip-flop (FF 3 or FF 13 ) together have a lower power consumption than the respective first delay flip-flop (FF 1 or FF 11 ) alone ( Fig. 7 and Fig. 11).