AU2002331580A1 - Method for reading a structural phase-change memory - Google Patents

Method for reading a structural phase-change memory

Info

Publication number: AU2002331580A1
Authority: AU; Australia
Prior art keywords: reading; change memory; structural phase; structural; phase
Prior art date: 2002-08-14
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Abandoned

Application number

AU2002331580A

Inventor

Tyler A. Lowrey

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Intel Corp

Original Assignee

Intel Corp

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

2002-08-14

Filing date

2002-08-14

Publication date

2004-03-03

2002-08-14 Application filed by Intel Corp filed Critical Intel Corp

2004-03-03 Publication of AU2002331580A1 publication Critical patent/AU2002331580A1/en

Status Abandoned legal-status Critical Current

Links

Classifications

- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/02—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
- G11C2013/0054—Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell

Landscapes

Chemical & Material Sciences (AREA)
Crystallography & Structural Chemistry (AREA)
Engineering & Computer Science (AREA)
Computer Hardware Design (AREA)
Semiconductor Memories (AREA)
Read Only Memory (AREA)

AU2002331580A 2002-08-14 2002-08-14 Method for reading a structural phase-change memory Abandoned AU2002331580A1 (en)

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
PCT/US2002/025932 WO2004017328A1 (en)	2002-08-14	2002-08-14	Method for reading a structural phase-change memory

Publications (1)

Publication Number	Publication Date
AU2002331580A1 true AU2002331580A1 (en)	2004-03-03

Family

ID=31886104

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
AU2002331580A Abandoned AU2002331580A1 (en)	2002-08-14	2002-08-14	Method for reading a structural phase-change memory

Country Status (5)

Country	Link
KR (1)	KR100634330B1 (en)
CN (1)	CN1628357B (en)
AU (1)	AU2002331580A1 (en)
DE (1)	DE10297767T5 (en)
WO (1)	WO2004017328A1 (en)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US6944041B1 (en) *	2004-03-26	2005-09-13	Bae Systems Information And Electronic Systems Integration, Inc.	Circuit for accessing a chalcogenide memory array
DE102004040753A1 (en) *	2004-08-23	2006-03-09	Infineon Technologies Ag	Circuit arrangement for information storage in cells of the CBRAM-type, has write transistor and constant current source arranged in symmetrical current circuit
DE102004041330B3 (en)	2004-08-26	2006-03-16	Infineon Technologies Ag	Memory circuit with a memory element having memory element resistance
DE102006016514A1 (en) *	2006-04-07	2007-10-18	Infineon Technologies Ag	Logic circuit e.g. dynamic programmable logic array, has NMOS-base transistor and two transistors, which are parallely arranged, where parameter of current flowing through NMOS-base transistor is determined by resistance values
JP5396011B2 (en) *	2007-06-19	2014-01-22	ピーエスフォールクスコエスエイアールエル	Phase change memory device
WO2009066204A1 (en) *	2007-11-22	2009-05-28	Nxp B.V.	Charge carrier stream generating electronic device and method
US7729163B2 (en) *	2008-03-26	2010-06-01	Micron Technology, Inc.	Phase change memory
US8027192B2 (en)	2008-08-20	2011-09-27	Samsung Electronics Co., Ltd.	Resistive memory devices using assymetrical bitline charging and discharging
KR101416834B1 (en) *	2008-08-20	2014-07-08	삼성전자주식회사	Nonvolatile memory device using variable resistive element
CN104600074A (en) *	2009-11-06	2015-05-06	株式会社半导体能源研究所	Semiconductor device
US8649212B2 (en) *	2010-09-24	2014-02-11	Intel Corporation	Method, apparatus and system to determine access information for a phase change memory
JP5598338B2 (en) *	2011-01-13	2014-10-01	ソニー株式会社	Storage device and operation method thereof
EP2684193B1 (en)	2011-03-10	2019-08-14	International Business Machines Corporation	Cell-state determination in phase-change memory
DE102012102326B4 (en) *	2012-03-20	2024-10-10	Helmholtz-Zentrum Dresden - Rossendorf E. V.	Method for producing an integrated non-volatile analog memory
US9520445B2 (en)	2011-07-12	2016-12-13	Helmholtz-Zentrum Dresden-Rossendorf E. V.	Integrated non-volatile memory elements, design and use
DE112012005424T5 (en) *	2011-12-21	2014-09-18	International Business Machines Corporation	Read / write operations in semiconductor memory devices
US10134470B2 (en)	2015-11-04	2018-11-20	Micron Technology, Inc.	Apparatuses and methods including memory and operation of same
US9530513B1 (en) *	2015-11-25	2016-12-27	Intel Corporation	Methods and apparatus to read memory cells based on clock pulse counts
US10446226B2 (en)	2016-08-08	2019-10-15	Micron Technology, Inc.	Apparatuses including multi-level memory cells and methods of operation of same
US10157670B2 (en) *	2016-10-28	2018-12-18	Micron Technology, Inc.	Apparatuses including memory cells and methods of operation of same
US10431301B2 (en)	2017-12-22	2019-10-01	Micron Technology, Inc.	Auto-referenced memory cell read techniques
US10566052B2 (en) *	2017-12-22	2020-02-18	Micron Technology, Inc.	Auto-referenced memory cell read techniques
WO2024060059A1 (en) *	2022-09-21	2024-03-28	Yangtze Advanced Memory Industrial Innovation Center Co., Ltd.	Memory device and controlling method thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
CN1206195A (en) *	1997-06-18	1999-01-27	日本电气株式会社	Semiconductor memory device with input/output masking function without destruction of data bit
US6314014B1 (en) *	1999-12-16	2001-11-06	Ovonyx, Inc.	Programmable resistance memory arrays with reference cells

2002
- 2002-08-14 AU AU2002331580A patent/AU2002331580A1/en not_active Abandoned
- 2002-08-14 WO PCT/US2002/025932 patent/WO2004017328A1/en not_active Application Discontinuation
- 2002-08-14 DE DE10297767T patent/DE10297767T5/en not_active Ceased
- 2002-08-14 CN CN02828593XA patent/CN1628357B/en not_active Expired - Fee Related
- 2002-08-14 KR KR1020047012320A patent/KR100634330B1/en active IP Right Grant

Also Published As

Publication number	Publication date
KR100634330B1 (en)	2006-10-16
WO2004017328A1 (en)	2004-02-26
KR20050018639A (en)	2005-02-23
CN1628357A (en)	2005-06-15
WO2004017328A8 (en)	2004-08-26
DE10297767T5 (en)	2005-08-04
CN1628357B (en)	2010-05-05

Legal Events

Date	Code	Title	Description
2005-04-28	MK6	Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase

Publication	Publication Date	Title
AU2002331580A1 (en)	2004-03-03	Method for reading a structural phase-change memory
AU2002363046A1 (en)	2003-05-06	Method for erasing a memory cell
AU2003213169A1 (en)	2003-12-12	Efficient read, write method for pipeline memory
AU2003211091A1 (en)	2003-10-27	Improved erase method for a dual bit memory cell
AU2003296988A1 (en)	2004-07-29	An improved method for making high-density nonvolatile memory
AU2003208489A1 (en)	2003-09-09	Method for desinging a well completion
HK1205275A1 (en)	2015-12-11	A method for addressing a bistable electro-optic medium
HK1113856A1 (en)	2008-10-17	A method for reproducing multi-angle data
IL154205A0 (en)	2003-07-31	Method for operating a memory device
AU2003256718A1 (en)	2004-06-30	Circuit for accurate memory read operations
AU2003222160A1 (en)	2003-10-27	Reading machine
AU2003228669A1 (en)	2003-12-12	Method of erasing a flashing memory using a pre-erasing step
AU2003205240A1 (en)	2003-09-16	Method for plugging selected cells in a honeycomb
AU2003206023A1 (en)	2003-09-09	Method for storing data blocks in a memory
EP1710701A4 (en)	2008-03-05	The method for managing the data in a removable memory
AU2003232038A1 (en)	2004-01-19	Memory having a precharge circuit and method therefor
AU2003273222A1 (en)	2004-06-23	Improved system for programming a non-volatile memory cell
AU2003201101A1 (en)	2003-09-02	Reading circuit for reading a memory cell
AU2003231220A1 (en)	2003-11-17	A method for detecting lysosomal storage diseases
AU2003249631A1 (en)	2003-11-11	Tester system having a multi-purpose memory
AU2003268019A1 (en)	2004-06-23	Improved pre-charge method for reading a non-volatile memory cell
EP1477903A3 (en)	2004-12-29	Memory system for a radiotelephone
AU2002354402A1 (en)	2003-06-23	Method for addressing a memory
GB2392749B (en)	2006-07-12	A method for changing computer system memory density
AU2003231259A1 (en)	2003-12-19	Method for collecting failure information for a memory using embedded test controller