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AU2001261207A1 - System and method for jitter compensation in data transfers - Google Patents

System and method for jitter compensation in data transfers

Info

Publication number
AU2001261207A1
AU2001261207A1 AU2001261207A AU6120701A AU2001261207A1 AU 2001261207 A1 AU2001261207 A1 AU 2001261207A1 AU 2001261207 A AU2001261207 A AU 2001261207A AU 6120701 A AU6120701 A AU 6120701A AU 2001261207 A1 AU2001261207 A1 AU 2001261207A1
Authority
AU
Australia
Prior art keywords
data transfers
jitter compensation
jitter
compensation
transfers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001261207A
Other languages
English (en)
Inventor
Thomas W. Bucht
Michael A. Nelson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Crossroads Systems Inc
Original Assignee
THOMAS W BUCHT
Crossroads Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by THOMAS W BUCHT, Crossroads Systems Inc filed Critical THOMAS W BUCHT
Publication of AU2001261207A1 publication Critical patent/AU2001261207A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
    • G06F5/14—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations for overflow or underflow handling, e.g. full or empty flags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/06—Indexing scheme relating to groups G06F5/06 - G06F5/16
    • G06F2205/062—Allowing rewriting or rereading data to or from the buffer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)
AU2001261207A 2000-05-08 2001-05-07 System and method for jitter compensation in data transfers Abandoned AU2001261207A1 (en)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US20272000P 2000-05-08 2000-05-08
US60/202,720 2000-05-08
US60202720 2000-05-08
US09/695,754 2000-10-24
US09/695,754 US6977897B1 (en) 2000-05-08 2000-10-24 System and method for jitter compensation in data transfers
US09695754 2000-10-24
PCT/US2001/014553 WO2001086449A2 (fr) 2000-05-08 2001-05-07 Systeme et procede de compensation de la gigue dans des transferts de donnees

Publications (1)

Publication Number Publication Date
AU2001261207A1 true AU2001261207A1 (en) 2001-11-20

Family

ID=26897963

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001261207A Abandoned AU2001261207A1 (en) 2000-05-08 2001-05-07 System and method for jitter compensation in data transfers

Country Status (3)

Country Link
US (1) US6977897B1 (fr)
AU (1) AU2001261207A1 (fr)
WO (1) WO2001086449A2 (fr)

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US8438601B2 (en) * 2003-07-02 2013-05-07 Rovi Solutions Corporation Resource management for a networked personal video recording system
JP4417807B2 (ja) * 2004-08-25 2010-02-17 株式会社東芝 エラスティックバッファ
JP4406838B2 (ja) * 2005-02-15 2010-02-03 ソニー株式会社 オーディオ入出力制御装置及びオーディオ入出力制御方法
US7672742B2 (en) * 2005-02-16 2010-03-02 Adaptec, Inc. Method and system for reducing audio latency
US8582946B2 (en) 2005-11-04 2013-11-12 Rovi Guides, Inc. Systems and methods for recording programs using a network recording device as supplemental storage
US7764614B2 (en) * 2005-11-15 2010-07-27 Lsi Corporation Multi-mode management of a serial communication link
US8726121B2 (en) * 2007-03-27 2014-05-13 Qualcomm Incorporated Circular buffer based rate matching
US20100138575A1 (en) 2008-12-01 2010-06-03 Micron Technology, Inc. Devices, systems, and methods to synchronize simultaneous dma parallel processing of a single data stream by multiple devices
US20100174887A1 (en) 2009-01-07 2010-07-08 Micron Technology Inc. Buses for Pattern-Recognition Processors
JP5229042B2 (ja) * 2009-03-25 2013-07-03 沖電気工業株式会社 ジッタバッファ制御装置、方法及びプログラム、並びに情報処理装置
US9323994B2 (en) 2009-12-15 2016-04-26 Micron Technology, Inc. Multi-level hierarchical routing matrices for pattern-recognition processors
US9075764B2 (en) * 2010-08-11 2015-07-07 Apple Inc. Multiprocessor system-on-a-chip for machine vision algorithms
US8680888B2 (en) * 2011-12-15 2014-03-25 Micron Technologies, Inc. Methods and systems for routing in a state machine
US20130275709A1 (en) 2012-04-12 2013-10-17 Micron Technology, Inc. Methods for reading data from a storage buffer including delaying activation of a column select
JP6113839B2 (ja) 2012-06-18 2017-04-12 クゥアルコム・インコーポレイテッドＱｕａｌｃｏｍｍ Ｉｎｃｏｒｐｏｒａｔｅｄ リングバッファに基づいたデータの適応オフセット同期（ａｄａｐｔｉｖｅｏｆｆｓｅｔｓｙｎｃｈｒｏｎｉｚａｔｉｏｎ）
US9524248B2 (en) 2012-07-18 2016-12-20 Micron Technology, Inc. Memory management for a hierarchical memory system
US9721495B2 (en) * 2013-02-27 2017-08-01 E Ink Corporation Methods for driving electro-optic displays
US9448965B2 (en) 2013-03-15 2016-09-20 Micron Technology, Inc. Receiving data streams in parallel and providing a first portion of data to a first state machine engine and a second portion to a second state machine
US9703574B2 (en) 2013-03-15 2017-07-11 Micron Technology, Inc. Overflow detection and correction in state machine engines
US10013375B2 (en) 2014-08-04 2018-07-03 Samsung Electronics Co., Ltd. System-on-chip including asynchronous interface and driving method thereof
WO2016109571A1 (fr) 2014-12-30 2016-07-07 Micron Technology, Inc Dispositifs de multiplexage par répartition dans le temps de signaux de moteur de machine à états
WO2016109570A1 (fr) 2014-12-30 2016-07-07 Micron Technology, Inc Systèmes et dispositifs pour accéder à un automate fini
US11366675B2 (en) 2014-12-30 2022-06-21 Micron Technology, Inc. Systems and devices for accessing a state machine
US10977309B2 (en) 2015-10-06 2021-04-13 Micron Technology, Inc. Methods and systems for creating networks
US10691964B2 (en) 2015-10-06 2020-06-23 Micron Technology, Inc. Methods and systems for event reporting
US10846103B2 (en) 2015-10-06 2020-11-24 Micron Technology, Inc. Methods and systems for representing processing resources
US10146555B2 (en) 2016-07-21 2018-12-04 Micron Technology, Inc. Adaptive routing to avoid non-repairable memory and logic defects on automata processor
US10268602B2 (en) 2016-09-29 2019-04-23 Micron Technology, Inc. System and method for individual addressing
US10019311B2 (en) 2016-09-29 2018-07-10 Micron Technology, Inc. Validation of a symbol response memory
US12197510B2 (en) 2016-10-20 2025-01-14 Micron Technology, Inc. Traversal of S portion of a graph problem to be solved using automata processor
US10592450B2 (en) 2016-10-20 2020-03-17 Micron Technology, Inc. Custom compute cores in integrated circuit devices
US10929764B2 (en) 2016-10-20 2021-02-23 Micron Technology, Inc. Boolean satisfiability
CN110557341A (zh) * 2018-05-31 2019-12-10 北京京东尚科信息技术有限公司 数据限流的方法和装置

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US6594329B1 (en) * 1999-11-01 2003-07-15 Intel Corporation Elastic buffer

Also Published As

Publication number Publication date
US6977897B1 (en) 2005-12-20
WO2001086449A2 (fr) 2001-11-15
WO2001086449A3 (fr) 2002-07-18

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