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Pomeranz et al., 2000 - Google Patents

Static test compaction for scan-based designs to reduce test application time

Pomeranz et al., 2000

Document ID
14141553779513291146
Author
Pomeranz I
Reddy S
Publication year
Publication venue
Journal of Electronic Testing

External Links

Snippet

We propose a static compaction procedure to reduce the test application time for full and partial scan synchronous sequential circuits. The procedure accepts as input a set of test subsequences. A test subsequence consists of a sequence of primary input vectors, and a …
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Classifications

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    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
    • G—PHYSICS
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    • G01R31/318583—Design for test
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    • G01R31/318371—Methodologies therefor, e.g. algorithms, procedures
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    • G01R31/318541—Scan latches or cell details
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    • G01R31/318566—Comparators; Diagnosing the device under test
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    • G01R31/31813—Test pattern generators
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    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
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    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. varying supply voltage
    • G—PHYSICS
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    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
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    • G—PHYSICS
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    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation

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