Eriksson et al., 2025 - Google Patents
Exploring the possibility of cracking Argon2 hashes with FPGA technologyEriksson et al., 2025
View PDF- Document ID
- 8846087012852995113
- Author
- Eriksson G
- Magnusson O
- Publication year
External Links
Snippet
As data security is continuously becoming more important to society, the interest in secure cryptographic hash functions is on the rise, as they play a vital role in the field. The winner of the Password Hashing Competition in 2015 was Argon2, which OWASP recommends as the …
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/77—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in smart cards
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/55—Detecting local intrusion or implementing counter-measures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/72—Indexing scheme relating to groups G06F7/72 - G06F7/729
- G06F2207/7219—Countermeasures against side channel or fault attacks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored programme computers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communication
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communication the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communication
- H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communication including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communication
- H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Pan et al. | An efficient elliptic curve cryptography signature server with GPU acceleration | |
| CN107851163A (en) | For the integrality of I/O data, anti-replay and the technology of authenticity guarantee | |
| Johnson et al. | Remote dynamic partial reconfiguration: A threat to Internet-of-Things and embedded security applications | |
| Fang et al. | Secure function evaluation using an fpga overlay architecture | |
| Mahmoud et al. | DFAulted: Analyzing and exploiting CPU software faults caused by FPGA-driven undervolting attacks | |
| Guo et al. | R/B-SecArch: A strong isolated SoC architecture based on red/black concept for secure and efficient cryptographic services | |
| Antognazza et al. | Metis: An integrated morphing engine CPU to protect against side channel attacks | |
| US12339959B2 (en) | Sparse encodings for control signals | |
| JP2024546936A (en) | Efficient and secure data processing using domain-aware masking | |
| Fang et al. | SIFO: Secure computational infrastructure using FPGA overlays | |
| Will et al. | Secure FPGA as a service—Towards secure data processing by physicalizing the cloud | |
| Mahmoud et al. | X-Attack 2.0: the risk of power wasters and satisfiability don’t-care hardware trojans to shared cloud FPGAs | |
| Saarinen | Simple AEAD hardware interface (SÆHI) in a SoC: implementing an on-chip Keyak/WhirlBob coprocessor | |
| Sunkavilli et al. | Dpredo: Dynamic partial reconfiguration enabled design obfuscation for fpga security | |
| Ciani et al. | Unleashing OpenTitan's Potential: a Silicon-Ready Embedded Secure Element for Root of Trust and Cryptographic Offloading | |
| Mühlbach et al. | Secure communication in microcomputer bus systems for embedded devices | |
| Asghar et al. | Increasing Side-Channel Resistance by Netlist Randomization and FPGA-Based Reconfiguration | |
| Eriksson et al. | Exploring the possibility of cracking Argon2 hashes with FPGA technology | |
| Conti et al. | Design exploration of aes accelerators on fpgas and gpus | |
| Jafarzadeh et al. | Real vulnerabilities in partial reconfigurable design cycles; case study for implementation of hardware security modules | |
| Fang | Privacy preserving computations accelerated using fpga overlays | |
| Schaumont et al. | Three design dimensions of secure embedded systems | |
| Costan et al. | Security challenges and opportunities in adaptive and reconfigurable hardware | |
| Kokila et al. | Hardware signature generation using a hybrid puf and fsm model for an soc architecture | |
| Thoonen | Hardening FPGA-based AES implementations against side channel attacks based on power analysis |