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Sivaswamy et al., 2007 - Google Patents

Variation-aware routing for FPGAs

Sivaswamy et al., 2007

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Document ID
7292881420722884501
Author
Sivaswamy S
Bazargan K
Publication year
Publication venue
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays

External Links

Snippet

Chip design in the nanometer regime is becoming increasingly difficult due to process variations. ASIC designers have adopted statistical optimization techniques to mitigate the effects of variations. The FPGA community on the other hand, has only recently started …
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Classifications

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    • G—PHYSICS
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    • G06F17/5072—Floorplanning, e.g. partitioning, placement
    • G—PHYSICS
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    • G—PHYSICS
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