Bondurant, 2024 - Google Patents

Scalable Control Architectures for Quantum Computing

Bondurant, 2024

Document ID: 6107708102284684266
Author: Bondurant B
Publication year: 2024

External Links

Cited by

Snippet

As performance gains in classical CPUs have slowed over time, the field of computing has looked to accelerators like the GPU as a solution. One such emerging technology is the quantum computer, leveraging the exotic properties of quantum mechanical systems to …

Continue reading at dukespace.lib.duke.edu (PDF) (other versions)

238000004422 calculation algorithm 0 abstract description 65

Classifications

- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/46—Multiprogramming arrangements
- G06F9/52—Programme synchronisation; Mutual exclusion, e.g. by means of semaphores; Contention for resources among tasks
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5061—Partitioning or combining of resources
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/44—Arrangements for executing specific programmes
- G06F9/455—Emulation; Software simulation, i.e. virtualisation or emulation of application or operating system execution engines
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
- G06F9/30087—Synchronisation or serialisation instructions
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored programme computers
- G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformations of program code
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/25—Using a specific main memory architecture

Similar Documents

Publication	Publication Date	Title
Mantovani et al.	2020	Agile SoC development with open ESP
Balkind et al.	2020	BYOC: a" bring your own core" framework for heterogeneous-ISA research
Giri et al.	2020	ESP4ML: Platform-based design of systems-on-chip for embedded machine learning
Mehta	2018	ASIC/SoC functional design verification
Bortolotti et al.	2013	Virtualsoc: A full-system simulation environment for massively parallel heterogeneous system-on-chip
Verhulst et al.	2011	Formal Development of a Network-Centric RTOS: software engineering for reliable embedded systems
Delbergue et al.	2016	QBox: an industrial solution for virtual platform simulation using QEMU and SystemC TLM-2.0
Matthews et al.	2020	MosaicSim: A lightweight, modular simulator for heterogeneous systems
Giri et al.	2020	Ariane+ NVDLA: Seamless third-party IP integration with ESP
Cabo et al.	2022	DVINO: A RISC-V vector processor implemented in 65nm technology
Silva et al.	2024	ChamelIoT: A tightly-and loosely-coupled hardware-assisted OS framework for low-end IoT devices
Malik et al.	2025	EPOCH: Enabling preemption operation for context saving in heterogeneous FPGA systems
Bondurant	2024	Scalable Control Architectures for Quantum Computing
Matthews et al.	2016	Shared memory multicore microblaze system with SMP linux support
Wu et al.	2021	A hardware platform for exploring predictable cache coherence protocols for real-time multicores
Bortolotti et al.	2016	VirtualSoC: A research tool for modern MPSoCs
Agne et al.	2016	ReconOS
Iordanou et al.	2019	Simacc: A configurable cycle-accurate simulator for customized accelerators on cpu-fpgas socs
Bathen et al.	2014	SPMCloud: Towards the single-chip embedded ScratchPad memory-based storage cloud
Haron et al.	2017	Internet of things platform on ARM/FPGA using embedded linux
Maaref	2022	Architecting and Building High-Speed SoCs
Tegegn	2019	An implementation of a predictable cache-coherent multi-core system
Nataraja	2023	A Research-Fertile Co-Emulation Framework for RISC-V Processor Verification
Aleem et al.	2016	A comparative study of heterogeneous processor simulators
Guerrieri et al.	2019	Snap-on user-space manager for dynamically reconfigurable system-on-chips