MUSKAN et al., 2023 - Google Patents
LOW POWER VLSI DESIGN AND FPGA IMPLEMENTATION OF VARIOUS MULTIPLIERSMUSKAN et al., 2023
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- 5563908938106996353
- Author
- MUSKAN A
- KHANAM R
- Publication year
- Publication venue
- JOURNAL OF TECHNICAL EDUCATION
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The vital role that function multipliers play in many different applications, including digital signal processing. The architecture of arithmetic multipliers must constantly change to achieve better performance. Technology development has led to the creation of a number of …
Classifications
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- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
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- G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
- G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
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- G06F7/523—Multiplying only
- G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
- G06F7/5318—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with column wise addition of partial products, e.g. using Wallace tree, Dadda counters
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