1. load from memory to Register
2. store from register to Memory
3. Add registers A1 and A2 and store them in A3 and A4
4. Multiply registers A1 and A2 and store them in A3 and A4

1. a Register file
2. a separate memory of consisting 512 units of 32bit words
3. an ALU for add and multiplication
4. A central Unit for connecting the foregoing modules and setting up the DataPath and ControlUnit

all these modules are described via verilog and the files are uploaded as well. also a documentation of the design is available. you can refer to vector_processor.pdf for a full documentation on how this processor performs.