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1. frizzle frizzle Public

   A RISC-V system simulator with VGA, UART, memory, and JTAG debugging, interconnected with SystemC/TLM, designed with operating systems and computer architecture classroom use in mind.

   C++ 13 3

2. riscv-dbg riscv-dbg Public

   Forked from pulp-platform/riscv-dbg

   RISC-V Debug Support for our PULP Cores

   SystemVerilog 1

3. jtag_vpi jtag_vpi Public

   Forked from fjullien/jtag_vpi

   TCP/IP controlled VPI JTAG Interface.

   Verilog

4. common_cells common_cells Public

   Forked from pulp-platform/common_cells

   Common SV components

   SystemVerilog 1

5. systemc systemc Public

   Forked from accellera-official/systemc

   Core SystemC Library

   C++

6. wbuart32 wbuart32 Public

   Forked from ZipCPU/wbuart32

   A simple, basic, formally verified UART controller

   Verilog