DNS stub resolver, proxy and router with support for DoT, DoH, DoQ, and DTLS

The Refreshingly Simple Cross-Platform C++ Dataflow / Patching / Pipelining / Graph Processing / Stream Processing / Reactive Programming Framework

Multi-device OpenCL kernel load balancer and pipeliner API for C#. Uses shared-distributed memory model to keep GPUs updated fast while using same kernel on all devices(for simplicity).

Cross-Platform Graphical Tool for DSPatch

Asynchronous, HA (master-master) PostgreSQL driver on top of libpq.

Implementation of pipelined IIR bandstop filter in Verilog, C++ and MATLAB with fixed point arithmetic

Efficiently pipeline, batch, and cache requests to any data source

Detailed and step by step implementation of RISC-V CPU from scratch using Verilog. This work is part of my academic course EE2003, Introduction to Computer Organisation in IIT Madras.

DSPatch Component Repository

A two-stage predictive machine learning engine that forecasts the on-time performance of flights for 15 different airports in the USA based on data collected in 2016 and 2017.

FluidML is a lightweight framework for developing machine learning pipelines.

A 5-stage pipelining RISC-V 32I simulator written in Rust.

An experiment in declaratively programming parallel pipelines of state machines.

Kite: Architecture Simulator for RISC-V Instruction Set

Design and verification of a simple pipelined RISC processor in Verilog, featuring a five-stage pipeline and custom ISA.

Educational computer simulator on a mission to "superscale" the study of computer architecture fundamentals

Have pipeline in Erlang

collection of scripts that chain together other scripts by preparing and processing/transforming data.

Package rpc implements a remote procedure call over TCP, UNIX, HTTP and WS. Up to 4x faster than net/rpc.

A pipers bag - generic functions to gain concurrency - batteries included :-)