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vhdl

Here are 2,818 public repositories matching this topic...

logisim-evolution

logisim-evolution / logisim-evolution

Digital logic design tool and simulator

education simulator fpga vhdl logic circuits verilog circuit digital-logic logisim digital-circuit digital-circuits timing-diagram digital-logic-design logisim-evolution

Updated Jul 8, 2025
Java

SpinalHDL / VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

cpu fpga vhdl riscv verilog soc spinalhdl softcore

Updated Jul 4, 2025
Assembly

ghdl / ghdl

VHDL 2008/93/87 simulator

simulator compiler hardware llvm vhdl gcc ghdl hacktoberfest testbench

Updated Jul 8, 2025
VHDL

cocotb / cocotb

cocotb: Python-based chip (RTL) verification

python test vhdl verification verilog uvm

Updated Jul 7, 2025
Python

SpinalHDL / SpinalHDL

Scala based HDL

scala fpga vhdl rtl verilog

Updated Jul 6, 2025
Scala

neorv32

stnolting / neorv32

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

microcontroller embedded cpu fpga processor vhdl riscv smp multi-core rtos hdl soc risc-v soft-core system-on-chip rv32 asip neorv32 on-chip-debbuger

Updated Jul 7, 2025
VHDL

clash-lang / clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

haskell asic fpga vhdl verilog systemverilog hardware-description-language

Updated Jul 8, 2025
Haskell

olofk / fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

python package-manager fpga vhdl eda verilog reuse

Updated Jun 19, 2025
Python

siliconcompiler / siliconcompiler

Modular hardware build system

asic fpga hls vhdl eda rtl verilog make synthesis cmos

Updated Jul 8, 2025
Python

drom / awesome-hdl

Hardware Description Languages

awesome vhdl verilog awesome-list hdl hacktoberfest hardware-description-language

Updated Feb 7, 2025

VUnit / vunit

VUnit is a unit testing framework for VHDL/SystemVerilog

unit-testing asic fpga vhdl verification testbench verilog-hdl systemverilog-hdl universal-verification-methodology

Updated May 11, 2025
VHDL

open-sdr / openwifi-hw

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

linux fpga zynq hls hardware vhdl rtl verilog xilinx sdr wi-fi analog-devices ieee80211 dma software-defined-radio ofdm csma ad9361 mac80211

Updated May 7, 2025
Verilog

nickg / nvc

VHDL compiler and simulator

simulator fpga compiler vhdl

Updated Jul 8, 2025
C

olofk / edalize

An abstraction library for interfacing EDA tools

Updated Jun 16, 2025
Python

antonblanchard / microwatt

A tiny Open POWER ISA softcore written in VHDL 2008

processor vhdl openpower ppc64le

Updated Apr 16, 2025
Verilog

sergeykhbr / riscv_vhdl

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

debugger qt simulator cpu vhdl riscv systemc soc

Updated Jun 24, 2025
Verilog

JulianKemmerer / PipelineC

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

python c fpga hls hardware vhdl pipelines open-source-hardware high-level-synthesis hardware-description-language fpga-accelerators fpga-acceleration fpga-programming hardware-description

Updated Jul 8, 2025
VHDL

TerosTechnology / vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

fpga vhdl verilog systemverilog

Updated Apr 4, 2025
VHDL

VLSI-EDA / PoC

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

Updated Nov 29, 2020
VHDL

ben-marshall / awesome-open-hardware-verification

A List of Free and Open Source Hardware Verification Tools and Frameworks

python coverage awesome hardware vhdl verification verilog awesome-list formal-verification constrained-random-verification

Updated Sep 8, 2023

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