A 2 stage CMOS OTA with Differential amplifier with active load as the first stage followed by Common Source stage using Cadence

A comprehensive VLSI design project implementing a static CMOS NAND gate using industry-standard Cadence tools and HSPICE simulation in 45nm technology.

A practical day-by-day journey exploring Digital IC Design using Cadence Virtuoso — from schematics to layouts, DRC/LVS checks, parasitic extraction, and timing analysis.