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1. chipyard chipyard Public

   Forked from ucb-bar/chipyard

   An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

   Scala

2. chipyard_fpga_genesys2 chipyard_fpga_genesys2 Public

   Add board support for Diligent Genesys2 for fpga prototyping (chipyard v1.13.0)

   C++ 3

3. u-boot u-boot Public

   Forked from u-boot/u-boot

   "Das U-Boot" Source Tree

   C

4. opensbi opensbi Public

   Forked from riscv-software-src/opensbi

   RISC-V Open Source Supervisor Binary Interface

   C

5. OSC-lab-kernel OSC-lab-kernel Public

   C

6. USB-BlackBox-demo USB-BlackBox-demo Public

   Testing USB IP using BlackBox in chipyard integrated with RISC-V SYSTEM

   Verilog