According to Tonc, DISPCNT Bit 5:

Allows access to OAM in an HBlank. OAM is normally locked in VDraw. Will reduce the amount of sprite pixels rendered per line.

This matches what GBATEK says:

Setting H-Blank Interval Free (Bit 5) allows to access OAM during H-Blank time - using this feature reduces the number of sprites that can be displayed per line.

However, this description is wrong!

There is no reason you can't access OAM at any point during VDraw (including HBlank) - it just might be a bit slower if you tried to do so at a moment when the PPU is accessing that memory.

Details from origamiscienceguy on Discord:

Vram, Palette, and OAM can be accessed at any time. If the PPU happens to be accessing something from that bank, waitstates will be inserted until an opening is available. This is usually just a couple cycles at most, with the exception of Mode 2 with both background enabled, in which case the PPU accesses the bg vram bank every cycle, forcing the CPU to wait until hblank to access.

The NanoBoyAdvance hardware docs explain the effect of Bit 5:

Sprite rendering for the current scanline starts at cycle #40 of the previous scanline and continues either until the horizontal blanking period of that previous scanline (if DISPCNT.bit5 = 1) or until cycle #40 of the current scanline (if DISPCNT.bit5 = 0).

In summary, enabling DISPCNT Bit 5 stops the PPU from accessing Obj-VRAM and OAM during HBlank, ensuring faster access to those memory areas at that time, but at the cost of reducing the number of sprite pixels that can be rendered per scanline.