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    • lwise

      Public
      RISC-V ISEs for NIST LWC submissions
      C
      0600Updated Apr 22, 2024Apr 22, 2024
    • rvkex

      Public
      Assembly
      0000Updated Mar 6, 2024Mar 6, 2024
    • texmf

      Public
      SCARV-related document preparation assets
      TeX
      0000Updated Feb 3, 2024Feb 3, 2024
    • eliminate

      Public
      eLIMInate: a Leakage-aware ISE for Masked Implementation
      SystemVerilog
      1300Updated Jan 31, 2024Jan 31, 2024
    • scarv-cpu

      Public archive
      SCARV: a side-channel hardened RISC-V platform
      Verilog
      52771Updated Jan 11, 2023Jan 11, 2023
    • sca3s-cli

      Public archive
      Python
      0000Updated Jan 11, 2023Jan 11, 2023
    • xcrypto

      Public archive
      XCrypto: a cryptographic ISE for RISC-V
      Verilog
      109280Updated Jan 5, 2023Jan 5, 2023
    • sca3s

      Public archive
      SCA3S: Side-Channel Analysis as a Service
      Shell
      0800Updated Nov 23, 2022Nov 23, 2022
    • sca3s-example

      Public archive
      SCA3S: Side-Channel Analysis as a Service
      C
      1000Updated Sep 8, 2022Sep 8, 2022
    • sca3s-backend

      Public archive
      SCA3S: Side-Channel Analysis as a Service
      Python
      0000Updated Aug 25, 2022Aug 25, 2022
    • theses

      Public archive
      SCARV-related UG, PGR, and PhD thesis archive
      3200Updated Aug 23, 2022Aug 23, 2022
    • sca3s-harness

      Public archive
      SCA3S: Side-Channel Analysis as a Service
      C
      3400Updated Aug 23, 2022Aug 23, 2022
    • hydra

      Public
      HYDRA: a multi-core RISC-V with cryptographically useful modes of operation
      Verilog
      2700Updated Jun 22, 2022Jun 22, 2022
    • HTML
      238000Updated Mar 15, 2022Mar 15, 2022
    • Crypto-supported ibex core verification
      C
      1100Updated Feb 22, 2022Feb 22, 2022
    • sca3s-middleware

      Public archive
      SCA3S: Side-Channel Analysis as a Service
      Python
      0000Updated Jan 17, 2022Jan 17, 2022
    • ibex

      Public
      Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
      SystemVerilog
      653000Updated Jan 4, 2022Jan 4, 2022
    • Verilog
      368100Updated Dec 6, 2021Dec 6, 2021
    • scarv-soc

      Public archive
      SCARV: a side-channel hardened RISC-V platform
      Verilog
      3551Updated Oct 29, 2021Oct 29, 2021
    • xdivinsa

      Public
      XDIVINSA: eXtended DIVersifying INStruction Agent to mitigate power side-channel leakage
      Verilog
      2200Updated Aug 6, 2021Aug 6, 2021
    • An Instruction Set Extension to accelerate ChaCha on 64-bit platforms, focusing on RISC-V
      TeX
      0100Updated Aug 5, 2021Aug 5, 2021
    • scaflow

      Public
      Python
      0200Updated Jul 21, 2021Jul 21, 2021
    • scarv

      Public archive
      SCARV: a side-channel hardened RISC-V platform
      Makefile
      42200Updated Mar 31, 2021Mar 31, 2021
    • libscarv

      Public archive
      libscarv: cryptographic software kernels for RISC-V
      C
      4620Updated Mar 31, 2021Mar 31, 2021
    • fw-acquisition

      Public archive
      SCARV Side channel AnalySis Suite test Rig - A flow for capturing and attacking power traces.
      Python
      0010Updated Feb 23, 2021Feb 23, 2021
    • Ways to accelerate AES in a RISC-like CPU pipeline.
      Verilog
      41000Updated Feb 12, 2021Feb 12, 2021
    • miracle

      Public archive
      MIRACLE: MIcRo-ArChitectural Leakage Evaluation
      C
      1730Updated Dec 11, 2020Dec 11, 2020
    • miracle-browser

      Public archive
      MIRACLE: MIcRo-ArChitectural Leakage Evaluation
      HTML
      3020Updated Dec 11, 2020Dec 11, 2020
    • miracle-db

      Public archive
      MIRACLE: MIcRo-ArChitectural Leakage Evaluation
      Python
      1000Updated Dec 11, 2020Dec 11, 2020
    • SCARV project fork of riscv/riscv-opcodes
      Python
      340000Updated Dec 9, 2020Dec 9, 2020
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