Repositories list

• OL-DFFRAM

  Public
  Pre-hardened DFFRAM macros using DFFRAM

  Verilog

  •

  Other

  •6•2•2•0•Updated Sep 29, 2025Sep 29, 2025

• volare

  Public
  Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKs

  pythonversion-managerpdk+ 2openlanepdks

  Python

  •

  Apache License 2.0

  •16•73•6•5•Updated Aug 9, 2025Aug 9, 2025

• chipcraft---mest-course

  Public
  TL-Verilog

  •

  Creative Commons Zero v1.0 Universal

  •14•37•0•0•Updated Jul 12, 2025Jul 12, 2025

• globalfoundries-pdk-libs-gf180mcu_fd_pr

  Public
  Primitives for GF180MCU provided by GlobalFoundries.

  Jupyter Notebook

  •

  Apache License 2.0

  •31•12•5•1•Updated Jul 6, 2025Jul 6, 2025

• caravel-sim-infrastructure

  Public
  HTML

  •

  Apache License 2.0

  •10•2•3•1•Updated Apr 24, 2025Apr 24, 2025

• chipignite_discover

  Public
  HTML

  •

  Apache License 2.0

  •7•2•0•0•Updated Mar 31, 2025Mar 31, 2025

• nldiff

  Public
  Simple netlist comparison utility

  Python

  •

  Apache License 2.0

  •3•6•0•1•Updated Mar 6, 2025Mar 6, 2025

• frigate_user_project

  Public
  Verilog

  •6•1•0•0•Updated Feb 28, 2025Feb 28, 2025

• timing-scripts

  Public
  Python

  •6•1•3•0•Updated Feb 28, 2025Feb 28, 2025

• IHP-Open-PDK

  Public
  130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design

  HTML

  •

  Apache License 2.0

  •110•5•1•0•Updated Feb 28, 2025Feb 28, 2025

• sky130_ef_ip__simple_por

  Public
  Simple PoR based on an RC filter

  Shell

  •

  Apache License 2.0

  •4•1•0•0•Updated Feb 26, 2025Feb 26, 2025

• sky130_ef_ip__adc3v_12bit

  Public
  12-bit ADC using other analog component repositories for the sample & hold, DAC, and comparator.

  Verilog

  •

  Apache License 2.0

  •6•2•0•0•Updated Feb 26, 2025Feb 26, 2025

• sky130_ef_ip__rdac3v_8bit

  Public
  8-bit resistor ladder DAC with 3.3V output range

  MATLAB

  •

  Apache License 2.0

  •6•1•0•0•Updated Feb 26, 2025Feb 26, 2025

• openlane-metrics

  Public
  Repository to store metric results for OpenLane 2.0.0+

  4•1•0•0•Updated Feb 26, 2025Feb 26, 2025

• caravel

  Public
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.

  magicyosyscaravel+ 5picorv32openroadvexriscvopenramsky130

  Verilog

  •

  Apache License 2.0

  •99•356•96•5•Updated Feb 26, 2025Feb 26, 2025

• openlane2

  Public
  The next generation of OpenLane, rewritten from scratch with a modular architecture

  flowasiceda+ 15verilogvlsipnrsiliconlvsflowssta+ 8

  Python

  •

  Apache License 2.0

  •68•315•91•6•Updated Feb 26, 2025Feb 26, 2025

• openlane2-step-unit-tests

  Public
  Step-specific Unit Tests for OpenLane 2.0.0+

  Verilog

  •

  Apache License 2.0

  •6•1•0•0•Updated Feb 26, 2025Feb 26, 2025

• EF_AES

  Public
  Verilog

  •5•1•1•1•Updated Feb 26, 2025Feb 26, 2025

• EF_PSRAM_CTRL

  Public
  Verilog

  •

  Apache License 2.0

  •6•6•3•1•Updated Feb 26, 2025Feb 26, 2025

• frigate-os

  Public
  Verilog

  •

  Apache License 2.0

  •13•6•0•0•Updated Feb 26, 2025Feb 26, 2025

• frigate_analog

  Public
  The analog signal processing and timing frontend subsystems for the Frigate harness chip

  Verilog

  •

  Apache License 2.0

  •4•1•1•1•Updated Feb 26, 2025Feb 26, 2025

• Caravel_on_FPGA

  Public
  Verilog

  •6•6•1•0•Updated Feb 25, 2025Feb 25, 2025

• mpw_precheck

  Public
  Python

  •

  Apache License 2.0

  •36•43•40•7•Updated Feb 25, 2025Feb 25, 2025

• caravel_user_project

  Public template
  https://caravel-user-project.readthedocs.io

  Verilog

  •

  Apache License 2.0

  •368•221•85•22•Updated Feb 25, 2025Feb 25, 2025

• sky130_ef_ip__samplehold

  Public
  Analog 3.3V sample and hold circuit, with buffered output

  Tcl

  •

  Apache License 2.0

  •5•0•0•0•Updated Feb 25, 2025Feb 25, 2025

• ipm

  Public
  Open-source IPs Package Manager (IPM)

  Python

  •

  Apache License 2.0

  •9•15•7•0•Updated Feb 24, 2025Feb 24, 2025

• nix-eda

  Public
  Nix derivations for EDA tools

  nixedaelectronic-design-automation+ 1nix-flake

  Nix

  •

  Apache License 2.0

  •8•11•3•0•Updated Feb 24, 2025Feb 24, 2025

• caravel_user_sram

  Public
  Verilog

  •

  Apache License 2.0

  •5•6•7•1•Updated Feb 24, 2025Feb 24, 2025

• sky130_ef_ip__template

  Public template
  A template repository for analog designs to ensure consistency and interoperability between IP blocks.

  Apache License 2.0

  •4•1•0•0•Updated Feb 24, 2025Feb 24, 2025

• EF_SRAM_1024x32

  Public
  Verilog

  •4•5•8•0•Updated Feb 23, 2025Feb 23, 2025