OpenTitan: Open source silicon root of trust

RISC-V Debug Support for our PULP Cores

Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

Random instruction generator for RISC-V processor verification

Verilator open-source SystemVerilog simulator and lint system

A self-contained cryptographic library for Python

TEMPORARY FORK of the riscv-compliance repository

An abstraction library for interfacing EDA tools

Fork of OpenOCD that has RISC-V support

Package manager and build abstraction tool for FPGA/ASIC development

lowRISC Style Guides

SAT solver for use in Enstaller, based on the MiniSat implementation

The OpenPiton Platform

Ariane is a 6-stage RISC-V CPU

Ariane SDK containing RISC-V tools and Buildroot

Common SV components

[UNRELEASED] Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

RISC-V Cores, SoC platforms and SoCs

Implementation of a RISC-V-compatible Platform Interrupt Controller (PLIC)

RISC-V Proxy Kernel

Classic multiplayer tetris for the terminal

AXI Adapter(s) for RISC-V Atomic Operations

AXI4 and AXI4-Lite interface definitions and testbench utilities

RISC-V Frontend Server

Coarse to fine Patch Match + Permeability Filter

IP Blocks to Support Design, Prototyping, and Verification of PULP on FPGAs

AXI X-Bar

Contains commonly used UVM components (agents, environments and tests).