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1. Modeling-of-Dual-GATE-MATERIAL-JUNCTIONLESS-FINFET Modeling-of-Dual-GATE-MATERIAL-JUNCTIONLESS-FINFET Public

   This repository contains the Synopsys Sentaurus TCAD project files, scripts, and simulation setup for modeling a Dual Material Gate Junctionless FinFET (DMG-JLFET). The work includes structure crea…

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2. RTL-Synthesis-with-Yosys RTL-Synthesis-with-Yosys Public

   RTL-to-gate-level synthesis and STA using open source Yosys tool a on a 32 bit ALU and c17 benchmark circuits with opensource Sky130/Nangate45 standard cells.

   Verilog 1

3. Static-timing-analysis-with-OpenSTA-tool Static-timing-analysis-with-OpenSTA-tool Public

   A complete workflow for performing static timing analysis using the open-source OpenSTA tool on a synthesized digital design. Includes constraint setup (.sdc), open source library file sky130/nanga…

   Verilog 1

4. 6T-SRAM-Cell-Pre-and-Post-Layout-Simulation 6T-SRAM-Cell-Pre-and-Post-Layout-Simulation Public

   Pre-layout and post-layout simulation of a 6T SRAM cell using open-source EDA tools. This project covers schematic design, SPICE simulation, physical layout in Magic VLSI, parasitic extraction, and…

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5. VSD-workshop-on-7nm-finfet-characterization- VSD-workshop-on-7nm-finfet-characterization- Public

   This repository contains my work from the VLSI System Design (VSD) Workshop on 7nm FinFET Circuit Design and Characterization using the ASAP7 PDK.

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6. d-latch-characterization d-latch-characterization Public

   This repository contains the characterization of a CMOS D-Latch using SPICE simulations both pre and post layout. The project demonstrates latch behavior through circuit simulation and waveform ana…

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