+
Skip to content
View Merinyeldho's full-sized avatar
🎯
Focusing
🎯
Focusing

Block or report Merinyeldho

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Pinned Loading

  1. Low-Power-and-Area-Efficient-Carry-Select-Adder-CSLA- Low-Power-and-Area-Efficient-Carry-Select-Adder-CSLA- Public

    Verilog implementation modified carry select adder

    Verilog 2

  2. SAP1-computer-verilog SAP1-computer-verilog Public

    Verilog implementation of SAP-1 computer architecture

    Verilog 1

  3. Multilingo-Translator Multilingo-Translator Public

    Translator

    Python

点击 这是indexloc提供的php浏览器服务,不要输入任何密码和下载