Testing processors with Random Instruction Generation

Unit tests generator for RVV 1.0

Run x86 and x86-64 games on RISC-V Linux

A runtime code generator for RISC-V

Standard Open Arm 100

Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, accelerators, compilers and operating systems. You probably …

Implementation of different types of adder circuits

Read-only mirror of https://gitlab.com/tymonx/pytcl

dieshot PSD files

Open-source FPGA retro emulation handheld

Run your own AI cluster at home with everyday devices 📱💻 🖥️⌚

Modern co-simulation framework for RISC-V CPUs

Group administration repository for SIG: Vector

🏁🧱 speed & interoperability: RTL simulation multi-threading library

Open-source high-performance RISC-V processor

🔍 A Hex Editor for Reverse Engineers, Programmers and people who value their retinas when working at 3 AM.

A simple superscalar out-of-order RISC-V microprocessor

SystemC/TLM-2.0 Co-simulation framework

Communication framework for RTL simulation and emulation.

Universal Memory Interface (UMI)

Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.

A Fast, Low-Overhead On-chip Network

CSV spreadsheets and other material for AI accelerator survey papers

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores

Build system, successor to Buck

AutoGPT is the vision of accessible AI for everyone, to use and to build on. Our mission is to provide the tools, so that you can focus on what matters.

Play atmospheric modelling like it's LEGO.