Stars
Leuvenshtein: Efficient FHE-based Edit Distance Computation with Single Bootstrap per Cell Rust implementation of our ASCII-based algorithm using TFHE-rs.
AXI, AXI stream, Ethernet, and PCIe components in System Verilog
An open source bike computer based on Raspberry Pi Zero (W, WH, 2W) with GPS and ANT+. Including offline map and navigation.
The simplest, fastest repository for training/finetuning medium-sized GPTs.
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
Performance-portable, length-agnostic SIMD with runtime dispatch
A web-based, unified, interactive bike map for NYC that combines information from NYC OpenData, Citi Bike and other sources.
QKeras: a quantization deep learning library for Tensorflow Keras
Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)
library for turning a RTL2832 based DVB dongle into a Software DefinedReceiver; mirror from https://gitea.osmocom.org/sdr/rtl-sdr
Compile Time Regular Expression in C++
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe
Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.
Vivado board files for the Kintex 7 HPC V2 FPGA board.
A utility to accurately report the in core memory usage for a program
SystemC/C++ library of commonly-used hardware functions and components for HLS.
Hardcaml is an OCaml library for designing hardware.
Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
TFHE: Fast Fully Homomorphic Encryption Library over the Torus