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  • Melbourne, VIC, Australia
  • 02:41 (UTC +11:00)
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6 results for source starred repositories written in Verilog
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PicoRV32 - A Size-Optimized RISC-V CPU

Verilog 3,778 878 Updated Jun 27, 2024

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our d…

Verilog 1,262 29 Updated Nov 19, 2025

A Pi emulating a GameBoy sounds cheap. What about an FPGA?

Verilog 507 61 Updated Dec 10, 2022

An attempt to recreate the RP2040 PIO in an FPGA

Verilog 305 31 Updated Jun 6, 2024

USB Serial on the TinyFPGA BX

Verilog 136 43 Updated Jun 20, 2021

这是我设计的第一个RV32内核,这个内核只打算实现RV32I指令集架构,对标8051及ARM Cortex-M0内核。This is the first RV32 core I designed. This core only intends to implement the RV32I instruction set architecture, which is aimed at the …

Verilog 8 1 Updated Feb 14, 2022