opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.

RISC-V 32bit single-cycle CPUs written in Logisim, Verilog, and Chisel

ao486 port for MiSTer

This is an attempt to make clean Verilog sources for each chip on the Amiga.

NeoGeo for MiSTer

Sega Genesis for MiSTer

A 16-bit RISC CPU with 32 instructions built with Digital for running on an FPGA.

Gameboy for MiSTer

Cycle-Accurate MC6809/E implementation, Verilog

Template with latest framework for MiSTer

Mega CD for MiSTer

Macintosh Plus for MiSTer

Atari ST/STe core for FPGAs

A RISC-V SoC ( Hbird e203 ) on Terasic DE10-Nano

Atari ST/STe for MiSTer

Acorn Archimedes for MiSTer

FPGA implementation of the TRS-80 Color Computer 3 in Verilog, by Gary Becker et al.

Arcade: Pacman for MiSTer

PDP-1 for MiSTer

Small micro-coded RISC-V softcore

Matra-Hachette Alice MC-10 for MiSTer FPGA

Apple I for MiSTer

LASER310 FPGA FLOPPY DD20 VZ200 VZ300 DE1 DE2 MC6847

6809 and 6309 Compatible core

CHIP-8 for MiSTer