This patch series greatly improve airoha snfi driver and fix a
number of serious bugs.

Fixed bugs:
 * Fix reading/writing of flashes with more than one plane per lun
 * Fill the buffer with 0xff before writing
 * Fix error paths

Improvements:
 * Add support of dual/quad wires spi modes in exec_op(). This also
   fix flash reading/writing if dirmap can't be created.
 * Support of dualio/quadio flash reading commands

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>

This patch series removes dirty hack that reads flash page settings from
SNFI registers during driver startup.

Before these patches the airoha spi snfi driver needs to know spinand
flash page size. The driver can't get it from spinand subsystem, so the
following approach was implemented:
 * bootloader know the flash page size (and some other parameters)
 * to operate properly the bootloader writes flash page size (and some
   other parameters) to SNFI registers
 * bootloader starts linux
 * after linux start SNFI registers keeps the values stored by bootloader
 * linux snfi driver reads flash parameters from SNFI registers.

This works, but we can do better. It has been proven that flash page size
is actually unnecessary. We can get all required data from dirmap requests.

This patch series drops the hack and do things properly.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>

This patch series greatly improve flash operation speed in u-boot.
The measurement shows:

With DMA:
  => mtd read.benchmark spi-nand0 $loadaddr 0 0x8000000
  Reading 134217728 byte(s) (65536 page(s)) at offset 0x00000000
  Read speed: 8131kiB/s

Without DMA:
  mtd read.benchmark spi-nand0 $loadaddr 0 0x8000000
  Reading 134217728 byte(s) (65536 page(s)) at offset 0x00000000
  Read speed: 2062kiB/s

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>

This patch removes dirty hack used to:
 * operate with flash
 * pass flash page settings to linux driver via SNFI registers

It has been proven that spinand flash page size is actually unnecessary.
We can get all required data from dirmap requests. Thus this patch
series drops the hack and do things properly.

After this fix (and corresponding linux fix) the hack is not needed
anymore.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>

This patch:
 * do not use dma acceleration for continuous reading mode (it's not
   supported by the driver)
 * fill the writing buffer gaps with 0xff to avoid data overwriting

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>

This patches just makes code better and mode ready for upstream

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>

mdio for embedded switch may not be probed, thus it will be not usable

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>

Changes:
 * an7581: add CONFIG_TARGET_AN7581=y
 * an758x: do not drop UBI redundand env

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>

Changes:
 * an7581: remove board specific mtd partitions from a common file
 * an7583: fix system controller node name

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>

The general idea is good, but the call of

  get_ram_size((void *)gd->ram_base, SZ_8G);

produces the following result on my an7581 board with only 1Gb of
memory:

  "Synchronous Abort" handler, esr 0x96000004
  elr: 0000000081e201c8 lr : 0000000081e20160 (reloc)
  elr: 00000000bff501c8 lr : 00000000bff50160
  x0 : 0000000180000000 x1 : 0000000100000000
  x2 : 000000000000002e x3 : 0000000000000002
  x4 : 000000001fbf0000 x5 : 0060000000000401
  x6 : 0000000000000000 x7 : 00000000bffdb268
  x8 : 0000000000000060 x9 : 00000000bffdb2c8
  x10: 0000000000000000 x11: 0000000000000060
  x12: 00000000bffdb268 x13: 00000000841c56d0
  x14: 00000000841c56d0 x15: 0000000000000000
  x16: 00000000841506e4 x17: dd7fe29aec3b07e8
  x18: 00000000bf710e00 x19: 0000000080000000
  x20: 0000000000000000 x21: 0000000020000000
  x22: 0000000200000000 x23: 0000000000000001
  x24: 0000000040000000 x25: 00000000bf708e78
  x26: 00000000bf7bdca0 x27: 0000000000000000
  x28: 0000000000000000 x29: 00000000bf708e20

  Code: 910943ff d65f03c0 d37df2a1 8b150e60 (f8616a62)
  Resetting CPU ...

So just not call get_ram_size() and use the value from dtb.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>

Usually U-Boot invoked during ATF BL33 stage, but sometimes it's maybe
desirable to run it on ATF BL31 stage.

Running during BL31 stage is mostly OK, but:
 * not-configured system timer put u-boot to infinite loop during almost
   any spinand flash operation
 * reset of the board is not possible because firmware with PSCI code
   is not loaded yet.

This patch series resolves above issues, so u-boot runs normally during
BL31 stage. These patches also a necessary step for using spinand driver
in U-Boot SPL/TPL (running as BL31)

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>