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Erik Hagersten
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- affiliation: Uppsala University, Sweden
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Journal Articles
- 2017
- [j9]Germán Ceballos
, Andra Hugo, Erik Hagersten, David Black-Schaffer:
Exploring Scheduling Effects on Task Performance with TaskInsight. Supercomput. Front. Innov. 4(3): 91-98 (2017) - 2016
- [j8]Konstantinos Koukos
Building Heterogeneous Unified Virtual Memories (UVMs) without the Overhead. ACM Trans. Archit. Code Optim. 13(1): 1:1-1:22 (2016) - [j7]Sam Van den Steen
Analytical Processor Performance and Power Modeling Using Micro-Architecture Independent Characteristics. IEEE Trans. Computers 65(12): 3537-3551 (2016) - 2015
- [j6]Mahdad Davari, Alberto Ros
The Effects of Granularity and Adaptivity on Private/Shared Classification for Coherence. ACM Trans. Archit. Code Optim. 12(3): 26:1-26:21 (2015) - 2009
- [j5]Dan Wallin, Henrik Löf, Erik Hagersten, Sverker Holmgren:
Reconsidering algorithms for iterative solvers in the multicore era. Int. J. Comput. Sci. Eng. 4(4): 270-282 (2009) - 2000
- [j4]Per Stenström, Erik Hagersten, David J. Lilja, Margaret Martonosi, Madan Venugopal:
Shared-memory multiprocessing: Current state and future directions. Adv. Comput. 53: 1-53 (2000) - 1999
- [j3]Erik Hagersten, Greg Papadopoulos:
Parallel computing in the commercial marketplace: research and innovation at work. Proc. IEEE 87(3): 405-411 (1999) - 1997
- [j2]Per Stenström, Erik Hagersten, David J. Lilja, Margaret Martonosi, Madan Venugopal:
Trends in Shared Memory Multiprocessing. Computer 30(12): 44-50 (1997) - 1992
- [j1]Erik Hagersten, Anders Landin, Seif Haridi:
DDM - A Cache-Only Memory Architecture. Computer 25(9): 44-54 (1992)
Conference and Workshop Papers
- 2019
- [c69]Nikos Nikoleris, Lieven Eeckhout, Erik Hagersten, Trevor E. Carlson:
Directed Statistical Warming through Time Traveling. MICRO 2019: 1037-1049 - 2018
- [c68]Germán Ceballos, Erik Hagersten, David Black-Schaffer:
Tail-PASS: Resource-Based Cache Management for Tiled Graphics Rendering Hardware. ISPA/IUCC/BDCloud/SocialCom/SustainCom 2018: 55-63 - 2017
- [c67]Andreas Sembrant, Trevor E. Carlson, Erik Hagersten, David Black-Schaffer:
POSTER: Putting the G back into GPU/CPU Systems Research. PACT 2017: 130-131 - [c66]Andreas Sembrant, Erik Hagersten, David Black-Schaffer:
A Split Cache Hierarchy for Enabling Data-Oriented Optimizations. HPCA 2017: 133-144 - [c65]Andreas Sembrant, Trevor E. Carlson, Erik Hagersten, David Black-Schaffer:
A graphics tracing framework for exploring CPU+GPU memory systems. IISWC 2017: 54-65 - [c64]Germán Ceballos
Understanding the interplay between task scheduling, memory and performance. SPLASH (Companion Volume) 2017: 21-23 - 2016
- [c63]Germán Ceballos
Formalizing Data Locality in Task Parallel Applications. ICA3PP Workshops 2016: 43-61 - [c62]Andreas Sembrant, Erik Hagersten, David Black-Schaffer:
Data placement across the cache hierarchy: Minimizing data movement with reuse-aware placement. ICCD 2016: 117-124 - [c61]Nikos Nikoleris, Andreas Sandberg
CoolSim: Eliminating traditional cache warming with fast, virtualized profiling. ISPASS 2016: 149-150 - [c60]Erik Hagersten:
Message from the general chair. ISPASS 2016: vi - [c59]Nikos Nikoleris, Andreas Sandberg
CoolSim: Statistical techniques to replace cache warming with efficient, virtualized profiling. SAMOS 2016: 106-115 - 2015
- [c58]Mahdad Davari, Alberto Ros
An Efficient, Self-Contained, On-chip Directory: DIR1-SISD. PACT 2015: 317-330 - [c57]Muneeb Khan, Michael A. Laurenzano, Jason Mars, Erik Hagersten, David Black-Schaffer:
AREP: Adaptive Resource Efficient Prefetching for Maximizing Multicore Performance. PACT 2015: 367-378 - [c56]Germán Ceballos
StatTask: reuse distance analysis for task-based applications. RAPIDO@HiPEAC 2015: 1:1-1:7 - [c55]Andreas Sandberg
Full Speed Ahead: Detailed Architectural Simulation at Near-Native Speed. IISWC 2015: 183-192 - [c54]Arthur Perais
Cost-effective speculative scheduling in high performance processors. ISCA 2015: 247-259 - [c53]Sam Van den Steen, Sander De Pestel, Moncef Mechri, Stijn Eyerman, Trevor E. Carlson
Micro-architecture independent analytical processor performance and power modeling. ISPASS 2015: 32-41 - [c52]Andreas Sembrant, Trevor E. Carlson
Long term parking (LTP): criticality-aware resource allocation in OOO processors. MICRO 2015: 334-346 - 2014
- [c51]Muneeb Khan, Andreas Sandberg
A Case for Resource Efficient Prefetching in Multicores. ICPP 2014: 101-110 - [c50]Andreas Sembrant, Erik Hagersten, David Black-Schaffer:
Navigating the cache hierarchy with a single lookup. ISCA 2014: 133-144 - [c49]Nikos Nikoleris
Extending statistical cache models to support detailed pipeline simulators. ISPASS 2014: 86-95 - [c48]Muneeb Khan, Andreas Sandberg
A case for resource efficient prefetching in multicores. ISPASS 2014: 137-138 - [c47]David Eklov, Nikos Nikoleris
A software based profiling method for obtaining speedup stacks on commodity multi-cores. ISPASS 2014: 148-157 - [c46]Muneeb Khan, Erik Hagersten:
Resource conscious prefetching for irregular applications in multicores. ICSAMOS 2014: 34-43 - 2013
- [c45]David Eklov, Nikos Nikoleris, David Black-Schaffer, Erik Hagersten:
Bandwidth Bandit: Quantitative characterization of memory contention. CGO 2013: 19:1-19:10 - [c44]Andreas Sandberg, Andreas Sembrant, Erik Hagersten, David Black-Schaffer:
Modeling performance variation due to cache sharing. HPCA 2013: 155-166 - [c43]Andreas Sembrant, Erik Hagersten, David Black-Schaffer:
TLC: a tag-less cache for reducing dynamic first level cache energy. MICRO 2013: 49-61 - 2012
- [c42]Andreas Sandberg
Efficient techniques for predicting cache sharing and throughput. PACT 2012: 305-314 - [c41]David Eklov, Nikos Nikoleris
Bandwidth bandit: quantitative characterization of memory contention. PACT 2012: 457-458 - [c40]Andreas Sembrant, David Black-Schaffer, Erik Hagersten:
Phase guided profiling for fast cache modeling. CGO 2012: 175-185 - [c39]Andreas Sembrant, David Black-Schaffer, Erik Hagersten:
Phase behavior in serial and parallel applications. IISWC 2012: 47-58 - [c38]David Eklov, Nikos Nikoleris
Bandwidth bandit: Understanding memory contention. ISPASS 2012: 116-117 - [c37]Bernd Mohr
The HOPSA Workflow and Tools. Parallel Tools Workshop 2012: 127-146 - [c36]Muneeb Khan, Andreas Sembrant, Erik Hagersten:
Low Overhead Instruction-Cache Modeling Using Instruction Reuse Profiles. SBAC-PAD 2012: 260-269 - 2011
- [c35]David Eklov, David Black-Schaffer, Erik Hagersten:
Fast modeling of shared caches in multicore systems. HiPEAC 2011: 147-157 - [c34]David Eklov, Nikos Nikoleris
Cache Pirating: Measuring the Curse of the Shared Cache. ICPP 2011: 165-175 - [c33]Andreas Sembrant, David Eklov, Erik Hagersten:
Efficient software-based online phase classification. IISWC 2011: 104-115 - 2010
- [c32]David Eklov, David Black-Schaffer, Erik Hagersten:
StatCC: a statistical cache contention model. PACT 2010: 551-552 - [c31]David Eklov, Erik Hagersten:
StatStack: Efficient modeling of LRU caches. ISPASS 2010: 55-65 - [c30]Andreas Sandberg
Reducing Cache Pollution Through Detection and Elimination of Non-Temporal Memory Accesses. SC 2010: 1-11 - 2008
- [c29]Erik Hagersten, Mats Nilsson, Magnus Vesterlund:
Improving Cache Utilization Using Acumem VPE. Parallel Tools Workshop 2008: 115-135 - 2007
- [c28]Martin Karlsson, Erik Hagersten:
Conserving Memory Bandwidth in Chip Multiprocessors with Runahead Execution. IPDPS 2007: 1-10 - [c27]Håkan Zeffer, Erik Hagersten:
A case for low-complexity MP architectures. SC 2007: 19 - 2006
- [c26]Dan Wallin, Henrik Löf, Erik Hagersten, Sverker Holmgren:
Multigrid and Gauss-Seidel smoothers revisited: parallelization on chip multiprocessors. ICS 2006: 145-155 - [c25]Håkan Zeffer, Zoran Radovic, Martin Karlsson, Erik Hagersten:
TMA: a trap-based memory architecture. ICS 2006: 259-268 - [c24]Pavlos Petoumenos
Modeling Cache Sharing on Chip Multiprocessor Architectures. IISWC 2006: 160-171 - [c23]Håkan Zeffer, Zoran Radovic, Erik Hagersten:
Exploiting locality: a flexible DSM approach. IPDPS 2006 - [c22]Erik Berg, Håkan Zeffer, Erik Hagersten:
A statistical multiprocessor cache model. ISPASS 2006: 89-99 - 2005
- [c21]Mathias Spjuth, Martin Karlsson, Erik Hagersten:
Skewed caches from a low-power perspective. Conf. Computing Frontiers 2005: 152-160 - [c20]Martin Karlsson, Erik Hagersten, Kevin E. Moore, David A. Wood:
Exploring Processor Design Options for Java-Based Middleware. ICPP 2005: 59-68 - [c19]Dan Wallin, Håkan Zeffer, Martin Karlsson, Erik Hagersten:
VASA: A Simulator Infrastructure with Adjustable Fidelity. IASTED PDCS 2005: 554-563 - [c18]Erik Berg, Erik Hagersten:
Fast data-locality profiling of native execution. SIGMETRICS 2005: 169-180 - 2004
- [c17]Håkan Zeffer, Zoran Radovic, Oskar Grenholm, Erik Hagersten:
Exploiting Spatial Store Locality Through Permission Caching in Software DSMs. Euro-Par 2004: 551-560 - [c16]Dan Wallin, Erik Hagersten:
Bundling: Reducing the Overhead of Multiprocessor Prefetchers. IPDPS 2004 - [c15]Erik Berg, Erik Hagersten:
StatCache: a probabilistic approach to efficient and accurate data locality analysis. ISPASS 2004: 20-27 - 2003
- [c14]Henrik Löf, Zoran Radovic, Erik Hagersten:
THROOM - Supporting POSIX Multithreaded Binaries on a Cluster. Euro-Par 2003: 760-769 - [c13]Martin Karlsson, Kevin E. Moore, Erik Hagersten, David A. Wood:
Memory System Behavior of Java-Based Middleware. HPCA 2003: 217-228 - [c12]Zoran Radovic, Erik Hagersten:
Hierarchical Backoff Locks for Nonuniform Communication Architectures. HPCA 2003: 241-252 - [c11]Dan Wallin, Erik Hagersten:
Miss Penalty Reduction Using Bundled Capacity Prefetching in Multiprocessors. IPDPS 2003: 12 - 2002
- [c10]Erik Berg, Erik Hagersten:
SIP: Performance Tuning through Source Code Interdependence. Euro-Par 2002: 177-186 - [c9]Zoran Radovic, Erik Hagersten:
Efficient synchronization for nonuniform communication architectures. SC 2002: 65:1-65:13 - 2001
- [c8]Zoran Radovic, Erik Hagersten:
Removing the overhead from software-based shared memory. SC 2001: 56 - 2000
- [c7]Erik Hagersten:
High-Performance Computers: Yesterday, Today, and Tomorrow. PARA 2000: 18 - 1999
- [c6]Erik Hagersten, Michael Koster:
WildFire: A Scalable Path for SMPs. HPCA 1999: 172-181 - 1994
- [c5]Erik Hagersten, Ashley Saulsbury, Anders Landin:
Simple COMA Node Implementations. HICSS (1) 1994: 522-533 - [c4]Peter S. Magnusson, Anders Landin, Erik Hagersten:
Queue Locks on Cache Coherent Multiprocessors. IPPS 1994: 165-171 - 1993
- [c3]Erik Hagersten, Mats Grindal, Anders Landin, Ashley Saulsbury, Bengt Werner, Seif Haridi:
Simulating the Data Diffusion Machine. PARLE 1993: 24-41 - 1991
- [c2]Anders Landin, Erik Hagersten, Seif Haridi:
Race-Free Interconnection Networks and Multiprocessor Consistency. ISCA 1991: 106-115 - 1989
- [c1]Seif Haridi, Erik Hagersten:
The Cache Coherence Protocol of the Data Diffusion Machine. PARLE (1) 1989: 1-18
Coauthor Index
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