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Volkan Kursun
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Publications
- 2011
- [j26]Sherif A. Tawfik, Volkan Kursun
:
Multi-Threshold Voltage FinFET Sequential Circuits. IEEE Trans. Very Large Scale Integr. Syst. 19(1): 151-156 (2011) - 2010
- [j22]Sherif A. Tawfik, Volkan Kursun
Dual Supply Voltages and Dual Clock Frequencies for Lower Clock Power and Suppressed Temperature-Gradient-Induced Clock Skew. IEEE Trans. Very Large Scale Integr. Syst. 18(3): 347-355 (2010) - 2009
- [j21]Sherif A. Tawfik, Volkan Kursun
Robust FinFET Memory Circuits with P-Type Data Access Transistors for Higher Integration Density and Reduced Leakage Power. J. Low Power Electron. 5(4): 497-508 (2009) - [j20]Ranjith Kumar, Volkan Kursun
Temperature-adaptive voltage scaling for enhanced energy efficiency in subthreshold memory arrays. Microelectron. J. 40(6): 1013-1025 (2009) - [j19]Sherif A. Tawfik, Volkan Kursun
FinFET domino logic with independent gate keepers. Microelectron. J. 40(11): 1531-1540 (2009) - [j18]Sherif A. Tawfik, Volkan Kursun
Low Power and High Speed Multi Threshold Voltage Interface Circuits. IEEE Trans. Very Large Scale Integr. Syst. 17(5): 638-645 (2009) - 2008
- [j17]Ranjith Kumar, Zhiyu Liu, Volkan Kursun
Technique for Accurate Power and Energy Measurement with the Computer-Aided Design Tools. J. Circuits Syst. Comput. 17(3): 399-421 (2008) - [j16]Ranjith Kumar, Volkan Kursun
Temperature-Adaptive Energy Reduction Techniques for Nano-CMOS Circuits Displaying Reversed temperature Dependence. J. Circuits Syst. Comput. 17(3): 423-438 (2008) - [j15]Sherif A. Tawfik, Volkan Kursun
Clock Distribution Networks with Gradual Signal Transition Time Relaxation for Reduced Power Consumption. J. Circuits Syst. Comput. 17(6): 1173-1191 (2008) - [j14]Ranjith Kumar, Volkan Kursun
Temperature-adaptive voltage tuning for enhanced energy efficiency in ultra-low-voltage circuits. Microelectron. J. 39(12): 1714-1727 (2008) - [j13]Zhiyu Liu, Volkan Kursun
Characterization of a Novel Nine-Transistor SRAM Cell. IEEE Trans. Very Large Scale Integr. Syst. 16(4): 488-492 (2008) - [c41]Sherif A. Tawfik, Volkan Kursun
Multi-Vth FinFET sequential circuits with independent-gate bias and work-function engineering for reduced power consumption. APCCAS 2008: 348-351 - [c40]Sherif A. Tawfik, Volkan Kursun
Asymmetric dual-gate multi-fin keeper bias options and optimization for low power and robust FinFET domino logic. APCCAS 2008: 1720-1723 - [c39]Sherif A. Tawfik, Volkan Kursun
Work-function engineering for reduced power and higher integration density: An alternative to sizing for stability in FinFET memory circuits. ISCAS 2008: 788-791 - [c38]Sherif A. Tawfik, Volkan Kursun
Low power and robust 7T dual-Vt SRAM circuit. ISCAS 2008: 1452-1455 - [c37]Sherif A. Tawfik, Volkan Kursun
Dynamic wordline voltage swing for low leakage and stable static memory banks. ISCAS 2008: 1894-1897 - [c36]Zhiyu Liu, Sherif A. Tawfik, Volkan Kursun
Statistical Data Stability and Leakage Evaluation of FinFET SRAM Cells with Dynamic Threshold Voltage Tuning under Process Parameter Fluctuations. ISQED 2008: 305-310 - [c35]Sherif A. Tawfik, Volkan Kursun
Characterization of New Static Independent-Gate-Biased FinFET Latches and Flip-Flops under Process Variations. ISQED 2008: 311-316 - [c34]Sherif A. Tawfik, Volkan Kursun
Compact FinFET Memory Circuits with P-Type Data Access Transistors for Low Leakage and Robust Operation. ISQED 2008: 855-860 - 2007
- [j12]Ranjith Kumar, Volkan Kursun
Voltage optimization for simultaneous energy efficiency and temperature variation resilience in CMOS circuits. Microelectron. J. 38(4-5): 583-594 (2007) - [j11]Zhiyu Liu, Volkan Kursun
PMOS-Only Sleep Switch Dual-Threshold Voltage Domino Logic in Sub-65-nm CMOS Technologies. IEEE Trans. Very Large Scale Integr. Syst. 15(12): 1311-1319 (2007) - [c33]Sherif A. Tawfik, Volkan Kursun
Low Power and Stable FinFET SRAM with Static Independent Gate Bias for Enhanced Integration Density. ICECS 2007: 443-446 - [c32]Sherif A. Tawfik, Volkan Kursun
Buffer Insertion and Sizing in Clock Distribution Networks with Gradual Transition Time Relaxation for Reduced Power Consumption. ICECS 2007: 845-848 - [c31]Zhiyu Liu, Volkan Kursun
New MTCMOS Flip-Flops with Simple Control Circuitry and Low Leakage Data Retention Capability. ICECS 2007: 1276-1279 - [c30]Ranjith Kumar, Volkan Kursun
Temperature-Adaptive Energy Reduction for Ultra-Low Power-Supply-Voltage Subthreshold Logic Circuits. ICECS 2007: 1280-1283 - [c29]Sherif A. Tawfik, Volkan Kursun
Low-Power Low-Voltage Hot-Spot Tolerant Clocking with Suppressed Skew. ISCAS 2007: 645-648 - [c28]Zhiyu Liu, Volkan Kursun
Charge Recycling MTCMOS for Low Energy Active/Sleep Mode Transitions. ISCAS 2007: 1389-1392 - [c27]Sherif A. Tawfik, Volkan Kursun
Multi-Vth Level Conversion Circuits for Multi-VDD Systems. ISCAS 2007: 1397-1400 - [c26]Zhiyu Liu, Volkan Kursun
High Read Stability and Low Leakage Cache Memory Cell. ISCAS 2007: 2774-2777 - [c25]Volkan Kursun
Leakage-Aware Design of Nanometer SoC. ISCAS 2007: 3231-3234 - [c24]Sherif A. Tawfik, Volkan Kursun
Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution. ISLPED 2007: 62-67 - [c23]Sherif A. Tawfik, Volkan Kursun
Dual-V_DD Clock Distribution for Low Power and Minimum Temperature Fluctuations Induced Skew. ISQED 2007: 73-78 - [c22]Zhiyu Liu, Volkan Kursun
Charge Recycling Between Virtual Power and Ground Lines for Low Energy MTCMOS. ISQED 2007: 239-244 - [c21]Zhiyu Liu, Sherif A. Tawfik, Volkan Kursun
An independent-gate FinFET SRAM cell for high data stability and enhanced integration density. SoCC 2007: 63-66 - [c20]Sherif A. Tawfik, Volkan Kursun
Low-power high-performance FinFET sequential circuits. SoCC 2007: 145-148 - 2006
- [j10]Zhiyu Liu, Volkan Kursun
Sleep switch dual threshold voltage domino logic with reduced subthreshold and gate oxide leakage current. Microelectron. J. 37(8): 812-820 (2006) - [j9]Zhiyu Liu, Volkan Kursun
Leakage Power Characteristics of Dynamic Circuits in Nanometer CMOS Technologies. IEEE Trans. Circuits Syst. II Express Briefs 53-II(8): 692-696 (2006) - [j8]Ranjith Kumar, Volkan Kursun
Reversed Temperature-Dependent Propagation Delay Characteristics in Nanometer CMOS Circuits. IEEE Trans. Circuits Syst. II Express Briefs 53-II(10): 1078-1082 (2006) - [j7]Zhiyu Liu, Volkan Kursun
Leakage Biased pMOS Sleep Switch Dynamic Circuits. IEEE Trans. Circuits Syst. II Express Briefs 53-II(10): 1093-1097 (2006) - [c19]Ranjith Kumar, Volkan Kursun
A design methodology for temperature variation insensitive low power circuits. ACM Great Lakes Symposium on VLSI 2006: 410-415 - [c18]Zhiyu Liu, Volkan Kursun
Leakage current starved domino logic. ACM Great Lakes Symposium on VLSI 2006: 428-433 - [c17]Ranjith Kumar, Volkan Kursun:
Impact of temperature fluctuations on circuit characteristics in 180nm and 65nm CMOS technologies. ISCAS 2006 - [c16]Volkan Kursun, Zhiyu Liu:
Wide temperature spectrum low leakage dynamic circuit technique for sub-65nm CMOS technologies. ISCAS 2006 - [c15]Zhiyu Liu, Volkan Kursun
Robust Dynamic Node Low Voltage Swing Domino Logic with Multiple Threshold Voltages. ISQED 2006: 31-36 - [c14]Zhiyu Liu, Volkan Kursun
Leakage Biased Sleep Switch Domino Logic. ISQED 2006: 318-323 - [c13]Zhiyu Liu, Volkan Kursun
High Speed Low Swing Dynamic Circuits with Multiple Supply and Threshold Voltages. ISVLSI 2006: 59-64 - [c12]Ranjith Kumar, Volkan Kursun
Supply and Threshold Voltage Optimization for Temperature Variation Insensitive Circuit Performance: A Comparison. SoCC 2006: 89-90 - [c11]Zhiyu Liu, Volkan Kursun
High Read Stability and Low Leakage SRAM Cell Based on Data/Bitline Decoupling. SoCC 2006: 115-116 - 2005
- [c9]Zhiyu Liu, Volkan Kursun
Shifted Leakage Power Characteristics of Dynamic Circuits Due to Gate Oxide Tunneling. SoCC 2005: 151-154
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